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US 10,707,199 B2Granted
Integrated circuit layout and method of configuring the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien
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Abstract
An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.
Claims20
An integrated circuit, comprising:
- a first cell having a first number of active areas, the active areas extending in a first longitudinal direction;
- a second cell adjacent said first cell in a second direction orthogonal to said first direction, wherein said second cell has a different number of active areas relative said first cell;
- said first cell having at least one first active area and at least one second active area, the at least one first active area and the at least one second active area being staggered relative to one another such that a first line in the second direction intersects both one first active area and one second active area and a second line in the second direction intersects one of but not both the one first active area and the one second active area;
- and
- said second cell having at least one third active area and at least one fourth active area, the at least one third active area and the at least one fourth active area being staggered relative to one another.
2 more elements
An integrated circuit comprising:
- a first plurality of p-type active regions, the first plurality of p-type active region all having a major axis extending in a first direction, being of same length in the first direction, and being adjacent one another;
- a second plurality of p-type active regions, the second plurality of p-type active region all having a major axis extending in the first direction, being of same length in the first direction, and being adjacent one another;
- a first gate electrode having a major axis extending in a second direction orthogonal to the first direction, the first gate electrode extending across respective mid-portions of the first plurality of p-type active regions;
- a second gate electrode aligned with the first gate electrode in the second direction, the second gate electrode extending across respective end-portions of the second plurality of p-type active regions;
- a third gate electrode having a major axis extending in the second direction, the third gate electrode extending across respective end-portions of the first plurality of p-type active regions;
- a fourth gate electrode aligned with the third gate electrode in the second direction, the fourth gate electrode extending across respective mid-portions of the second plurality of p-type active regions;
- a first plurality of n-type active regions, the first plurality of n-type active regions being aligned with the first plurality of p-type active regions in the first direction;
- a second plurality of n-type active regions, the second plurality of n-type active regions being aligned with the second plurality of p-type active regions in the first direction;
- a fifth gate electrode having a major axis extending in the second direction, the fifth gate electrode extending across respective mid-portions of the first plurality of n-type active regions;
- a sixth gate electrode aligned with the fifth gate electrode in the second direction, the sixth gate electrode extending across respective end-portions of the second plurality of n-type active regions;
- a seventh gate electrode having a major axis extending in the second direction, the seventh gate electrode extending across respective end-portions of the first plurality of n-type active regions;
- and
- an eighth gate electrode aligned with the seventh gate electrode in the second direction, the eighth gate electrode extending across respective mid-portions of the second plurality of n-type active regions.
10 more elements
An integrated circuit comprising:
- a first active region having a major axis extending in a first direction, the first active region having a first end and a second end;
- a second active region adjacent to the first active region, the second active region having a major axis extending in the first direction and having a third end and a fourth end, wherein the first end of the first active region extends further in the first direction than the third end of the second active region and further wherein the fourth end of the second active region extends further in the first direction than the second end of the first active region;
- a first gate electrode layer having a major axis extending in a second direction different than the first direction and including a gap separating the first gate electrode layer into a first gate electrode extending over a mid-portion of the first active region and a second gate electrode extending over the third end of the second active region;
- a second gate electrode layer having a major axis extending in the second direction and offset from the first gate electrode in the first direction, the second gate electrode layer including a second gap separating the second gate electrode layer into a third electrode extending over a mid-portion of the second active region and a fourth gate electrode extending over the second end of the first active region;
- and
- at least one third active region adjacent to and substantially aligned with the first active region.
3 more elements
Dependencies are inferred from the claim text.