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US 10,707,183 B2Granted
Flip chip package utilizing trace bump trace interconnection
AssigneeMediatek Inc.
InventorsTzu-Hung Lin, Thomas Matthew Gregorich
Life of this patent
Estimating the term…
Abstract
A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.
Claims20
A flip chip package, comprising:
- a substrate having a die attach surface;
- and
- a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface, wherein at least one of the plurality of conductive pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate, and wherein the at least one of the plurality of conductive pillar bumps is directly jointed to the trace, wherein the conductive pillar bump has a lower stress side that is closer to a center of the die and a higher stress side that is father away from the center of the die along a lengthwise direction, wherein the conductive pillar bump comprises an asymmetric plug configuration along the lengthwise direction, and wherein the asymmetric plug configuration comprises an integral plug disposed on the lower stress side of the conductive pillar bump along the lengthwise direction.
A flip chip package, comprising:
- a substrate having a die attach surface;
- and
- a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface, wherein at least one of the plurality of conductive pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate, and wherein no substrate via is interposed between the at least one of the plurality of conductive pillar bumps and the trace, wherein the conductive pillar bump has a lower stress side that is closer to a center of the die and a higher stress side that is father away from the center of the die along a lengthwise direction, wherein the conductive pillar bump comprises an asymmetric plug configuration along the lengthwise direction, and wherein the asymmetric plug configuration comprises an integral plug disposed on the lower stress side of the conductive pillar bump along the lengthwise direction.
Dependencies are inferred from the claim text.