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US 10,707,166 B2Granted
Advanced metal interconnects
AssigneeInternational Business Machines Corporation
InventorChih-Chao Yang
Life of this patent
Estimating the term…
Abstract
A method of fabricating a metallization layer of a semiconductor device in which one or more interconnect structures are to be formed includes depositing a dielectric layer and forming a trench for each interconnect structure to be formed in the metallization layer. An insulating liner layer is deposited that serves both as a metal diffusion barrier and as a metal adhesion layer for the interconnect structures.
Claims16
A method, comprising:
- in a fabrication stage of a metallization layer of a semiconductor device in which one or more interconnect structures are to be formed, initially depositing a dielectric layer as a basis for said metallization layer;
- forming a trench in said dielectric layer for each interconnect structure to be formed in said metallization layer;
- and
- depositing an insulating liner layer that serves both as a metal diffusion barrier and as a metal adhesion layer for said interconnect structures,
- wherein said insulating liner layer comprises one of Ta3N5 and M(N,O), where M is any of Ta, Ti, Mn, Ni, W, Hf, Mg, Cr, Ga, V, Co, and Cu.
2 more elements
A semiconductor device, comprising:
- a substrate having a plurality of electronic component elements fabricated on a top surface thereof, in a device layer;
- and
- a plurality of metallization layers formed successively on top of said device layer, to interconnect said electronic component elements, each said metallization layer having a different interconnect pattern,
- wherein at least one metallization layer includes one or more interconnect structures formed in a dielectric layer, and at least one said interconnect structures comprises:
- a fill metal;
- and
- an insulating liner layer that surrounds said fill metal on sides and bottom in a cross-sectional view and that serves both as a metal diffusion barrier and as a metal adhesion layer for said interconnect structure,
- wherein a size of metal grains at a top portion of said interconnect structure in said cross sectional view is larger than a size of metal grains at a bottom portion of said interconnect structure, and
- wherein said insulating liner layer comprises one of Ta3N5 and M(N,O), where M is any of Ta, Ti, Mn, Ni, W, Hf, Mg, Cr, Ga, V, Co, and Cu.
6 more elements
Dependencies are inferred from the claim text.