Back to results
US 10,707,162 B2Granted
Metal-on-metal capacitors
AssigneeApple Inc.
InventorsYi Chun A. Fu, Mansour Keramat, Vijay Srinivas
Life of this patent
Estimating the term…
Abstract
Capacitor structures with pitch-matched capacitor unit cells are described. In an embodiment, the capacitor unit cells are formed by interdigitated finger electrodes. The finger electrodes may be pitch-matched in multiple metal layers within a capacitor unit cell, and the finger electrodes may be pitch-matched among an array of capacitor unit cells. Additionally, border unit cells may be pitch-matched with the capacitor unit cells.
Claims18
A capacitor structure comprising:
- an array of capacitor unit cells arranged in a plurality of rows of capacitor unit cells and a plurality of columns of capacitor unit cells;
- wherein each capacitor unit cell of the array of capacitor unit cells comprises a lower metal layer including a first plurality of finger electrodes interdigitated with a second plurality of finger electrodes, and an upper metal layer including a third plurality of finger electrodes interdigitated with a fourth plurality of finger electrodes;
- and
- wherein the array of capacitor unit cells comprises a plurality of main capacitor unit cells, and a plurality of capacitor sub-unit cells, each capacitor main unit cell and each capacitor sub-unit cell characterized by an approximately equivalent via density between the lower metal layer and the upper metal layer.
1 more element
An analog-to-digital (ADC) converter comprising:
- a successive approximation register (SAR);
- a digital-to-analog converter (DAC);
- a plurality of digital logic bit nodes that connect the SAR to the DAC;
- and
- comparator circuit connected to a floating node of the DAC;
- wherein the DAC includes an array of capacitor unit cells arranged in a plurality of rows of capacitor unit cells and a plurality of columns of capacitor unit cells, and wherein each capacitor unit cell of the array of capacitor unit cells comprises a metal layer including a first plurality of finger electrodes interdigitated with a second plurality of finger electrodes;
- a plurality of rows of common rails extending through the plurality of rows of capacitor unit cells and electrically coupled with a portion of the first plurality of finger electrodes;
- a plurality of columns of common rails extending through the plurality of columns of capacitor unit cells and electrically coupled with a portion of the second plurality of finger electrodes;
- wherein each common rail extending through a column of capacitor unit cells is coupled to a corresponding digital logic bit node of the plurality of digital logic bit nodes, and each common rail extending through a row of capacitor unit cells is coupled to the floating node.
6 more elements
A capacitor structure comprising:
- an array of capacitor unit cells arranged in a plurality of rows of capacitor unit cells and a plurality of columns of capacitor unit cells;
- wherein each capacitor unit cell of the array of capacitor unit cells comprises a lower metal layer including a first a first plurality of finger electrodes interdigitated with a second plurality of finger electrodes;
- and
- a plurality of rows of common rails extending through the plurality of rows of capacitor unit cells and electrically coupled with a portion of the first pluralities of finger electrodes;
- a plurality of columns of common rails extending through the plurality of columns of capacitor unit cells and electrically coupled with a portion of the second pluralities of finger electrodes;
- wherein each common rail extending through a column of capacitor unit cells is coupled to a corresponding digital logic bit node, and each common rail extending through a row of capacitor unit cells is coupled to a floating node.
3 more elements
Dependencies are inferred from the claim text.