Back to results
US 10,707,131 B2Granted
Semiconductor device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPeng-Soon Lim, Zi-Wei Fang
Life of this patent
Estimating the term…
Abstract
A method includes forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate; patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure including a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer; forming a plurality of first gate spacers on opposite sides of the first stacked structure; removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer; and forming a first work function metal layer on the first portion of the metallic capping layer.
Claims20
A method, comprising:
- forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate;
- patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure comprising a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer and a second stacked structure comprising a second portion of the metallic capping layer and a second portion of the dummy gate electrode layer;
- forming a plurality of first gate spacers on opposite sides of the first stacked structure and a plurality of second gate spacers on opposite sides of the second stacked structure;
- forming a mask layer covering the second stacked structure and exposing the first stacked structure;
- removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer;
- selectively forming a first work function metal layer on the first portion of the metallic capping layer, wherein sidewalls of the first gate spacers remain exposed after forming the first work function metal layer;
- removing the mask layer to expose the second stacked structure;
- removing the second portion of the dummy gate electrode layer to expose the second portion of the metallic capping layer;
- and
- selectively forming a second work function metal layer on the first work function metal layer and the second portion of the metallic capping layer, wherein sidewalls of the first gate spacers and the second gate spacers remain exposed after forming the second work function metal layer.
7 more elements
A method, comprising:
- forming a first dummy gate structure over a semiconductor substrate;
- forming a plurality of first gate spacers on opposite sides of the first dummy gate structure;
- replacing the first dummy gate structure with a first metal gate structure, wherein the first metal gate structure comprises a gate dielectric and a work function metal layer over the gate dielectric;
- etching back the work function metal layer of the first metal gate structure to a level lower than tops of the first gate spacers and a top of the gate dielectric, while leaving the gate dielectric of the first metal gate structure covering sidewalls of the first gate spacers;
- and
- depositing a metal layer on the first metal gate structure such that the gate dielectric of the first metal gate structure is between the metal layer and the first gate spacers, wherein a deposition rate of the metal layer on a top surface of the first metal gate structure is faster than a deposition rate of the metal layer on sidewalls of the first gate spacers.
3 more elements
A method, comprising:
- forming a first dummy gate structure and a second dummy gate structure over a substrate, wherein a width of the first dummy gate structure is lower than a width of the second dummy gate structure;
- forming first gate spacers on opposite sidewalls of the first dummy gate structure and forming second gate spacers on opposite sidewalls of the second dummy gate structure;
- removing the first dummy gate structure and the second dummy gate structure to form a first gate trench between the first gate spacers and a second gate trench between the second gate spacers;
- depositing a work function metal layer in the first gate trench and the second gate trench;
- depositing a filling metal over the work function metal layer;
- performing a first CMP process to the filling metal, such that a portion of the filling metal remains in the second gate trench, wherein the remaining portion has a recess;
- and
- selectively depositing a metal layer in the recess of the remaining portion of the filling metal.
5 more elements
Dependencies are inferred from the claim text.