Solid state memory device, and manufacturing method thereof

A conductive structure, comprising:

• an interconnect;
• a plurality of conductive layers having a first portion in a periphery region overlying the interconnect and a second portion in at least one of a memory array region or a staircase region, wherein a material of the first and second portions of the plurality of conductive layers is the same material, each conductive layer being separated from an adjacent conductive layer by an insulative layer;
• a barrier having a wall configuration, the first and second portions of the plurality of conductive layers being separated from one another by the barrier;
• a contact extending through the first portion of the plurality of conductive layers to the interconnect, wherein the contact is electrically coupled to the interconnect and insulated from the first portion of the plurality of conductive layers;
• and
• an insulative liner having a plurality of insulative liner layers disposed about the contact between the contact and the conductive and insulative layers to insulate the contact from the conductive layers.