Semiconductor memory devices and methods of operating semiconductor memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsSeok-Jin Cho, Tae-Young Oh, Jung-Hwan Park
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Abstract
A semiconductor memory device includes a memory cell array and an address decoder. The memory cell array includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word-lines and bit-lines, each of the plurality of memory blocks are divided into a plurality of row blocks by row block identity bits of a row address, and each of the of row blocks includes a plurality of sub-array blocks arranged in a first direction. The address decoder changes a physical row address of a memory cell that stores or outputs data based on a column address received with a write command or a read command.
Claims20
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of dynamic memory cells coupled to word-lines and bit-lines, wherein each of the plurality of memory blocks are divided into a plurality of row blocks by at least one row block identity bit corresponding to a portion of bits of a row address, and each of the row blocks includes a plurality of sub-array blocks arranged in a first direction;
- a row decoder configured to activate a first word-line in a first row block of the plurality of row blocks in response to the row address, configured to activate a second word-line in a second row block of the plurality of row blocks, the second row block being different from the first row block, when the first row block includes at least one defective cell, and configured to output a row block information signal indicating whether the second word-line is activated, wherein the first row block is associated with a first segment of a plurality of segments, the second row block is associated with a second segment of the plurality of segments, the second segment being different from the first segment, and the plurality of memory blocks are divided into the plurality of segments in a second direction crossing the first direction;
- and
- a column decoder configured to receive the row block information signal and to repair a first bit-line coupled to the at least one defective cell with one of a first spare bit-line in the first segment and a second spare bit-line in the second segment in response to a column address and the row block information signal.
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of dynamic memory cells coupled to word-lines and bit-lines, wherein each of the plurality of memory blocks is divided into a plurality of row blocks by row block identity bits corresponding to a portion of bits of a row address, and each of the row blocks includes a plurality of sub-array blocks arranged in a first direction;
- and
- an address decoder configured to change a physical row address of a memory cell that stores or outputs data based on a column address received with a write command or a read command,
- wherein the address decoder includes:
- a row decoder configured to activate a first word-line in a first row block of the plurality of row blocks in response to the row address, configured to activate a second word-line in a second row block of the plurality of row blocks when the first row block includes at least one defective cell and configured to output a row block information signal indicating that the second word-line is activated, wherein the first row block is associated with a first segment of a plurality of segments, the second row block is associated with a second segment of the plurality of segments different from the first segment, and the plurality of memory blocks are divided into the plurality of segments in a second direction crossing the first direction;
- and
- a column decoder configured to receive the row block information signal output from the row decoder and to repair a first bit-line coupled to the at least one defective cell with one of a first spare bit-line in the first segment and a second spare bit-line in the second segment in response to a column address and the row block information signal.
A method of operating a semiconductor memory device, wherein the semiconductor memory device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of dynamic memory cells coupled to word-lines and bit-lines, wherein each of the plurality of memory blocks is divided into a plurality of row blocks by a row block identity bit corresponding to a portion of bits of a row address, and each of the row blocks includes a plurality of sub-array blocks arranged in a first direction, the method comprising:
- activating, by a row decoder, a first word-line in a first row block of the plurality of row blocks in response to the row address;
- activating a second word-line in a second row block of the plurality of row blocks different from the first row block when the first row block includes at least one defective cell;
- outputting by the row decoder, a row block information signal indicating that the second word-line in the second row block has been activated;
- receiving, by a column decoder, the row block information signal;
- and
- repairing, by the column decoder, a first bit-line coupled to the at least one defective cell with one of a first spare bit-line in a first segment of a plurality of segments and a second spare bit-line in a second segment of the plurality of segments in response to a column address and the row block information signal,
- wherein the row block information signal indicates that the first row block includes the at least one defective cell.
Dependencies are inferred from the claim text.