Back to results
US 10,706,952 B1Granted
Testing for memories during mission mode self-test
AssigneeCadence Design Systems, Inc.
InventorsSteven Lee Gregor, Patrick Gallagher
Life of this patent
Estimating the term…
Abstract
Systems and methods disclosed herein provide for efficiently testing memories during mission mode self-test (“MMST”) without destroying any original functional data. Embodiments provide for a converter to feed a manipulated version of the original functional data back into the tested memories. Embodiments further provide an accumulator to count the occurrences of correctable and uncorrectable errors associated with the tested memories.
Claims20
A memory built-in self-test (MBIST) diagnostics system comprising:
- at least one physical memory;
- MBIST logic comprising:
- an algorithm memory unit (AMU) configured to store at least one memory test program;
- at least one sequence iterator unit (SIU) configured to receive the at least one memory test program from the AMU one line at a time, to generate a command and address sequence based on the received line of the at least one memory test program, to generate an MBIST select signal, and to transmit expected data;
- at least one data compare unit (DCU) configured to receive the expected data from the at least one SIU, to compare the expected data with read data, to generate at least one result signal based on the comparison, and to transmit the at least one result signal at least to the at least one SIU;
- and
- an accumulator configured to accumulate an error count based on the result signal;
- a converter configured to perform a reversible transformation on at least one data word;
- three physical module multiplexers, including a data-in physical module multiplexer, an address physical module multiplexer, and a control physical module multiplexer, each physical module multiplexer configured to receive the MBIST select signal as a multiplexer selection signal to select between different data inputs of each physical module multiplexer;
- error correction code (ECC) encoder circuitry coupled to a write input of the at least one physical memory via the data-in physical module multiplexer;
- ECC checker circuitry coupled to a read output of the at least one physical memory, the at least one physical memory, ECC encoder, and ECC checker forming a logical memory;
- and
- at least three logical module multiplexers, including at least a data-in logical module multiplexer, an address logical module multiplexer, and a control logical module multiplexer, the data-in logical module multiplexer configured to selectively pass to the ECC encoder circuitry a data-in signal from one of functional logic, the MBIST logic, or the converter, the address and control logical module multiplexers configured to selectively pass to the address and control physical module multiplexers address and control signals, respectively, from one of the functional logic or the MBIST logic, each logical module multiplexer configured to receive the MBIST select signal as a multiplexer selection signal to select between different data inputs of each logical module multiplexer,
- the converter having a control input coupled to the MBIST logic, a data input coupled to a data-out output of the logical memory, and a data output coupled to a data input of the data-in logical module multiplexer,
- the MBIST logic having data-in, address, and control outputs coupled to the physical module multiplexers and the logical module multiplexers, and
- the MBIST select signal configuring the MBIST diagnostics system between one of a test of the at least one physical memory, a test of the logical memory, a functional operation test, or a non-test mode.
13 more elements
A diagnostics method for a memory built-in self-test (MBIST), the method comprising:
- selecting, based on an MBIST select signal, one from among of a group comprising (i) a test of at least one physical memory, (ii) a test of a logical memory comprising the at least one physical memory and error correction code (ECC) encoder circuitry and ECC checker circuitry, (iii) a functional operation test, or (iv) a non-test mode;
- based on the selection of the test of the at least one physical memory, configuring physical module multiplexers to pass write data and address and control signals to the at least one physical memory from MBIST logic, and configuring the MBIST logic to receive read data from the at least one physical memory, bypassing the ECC encoder and checker circuitry;
- based on the selection of the test of the logical memory, configuring logical module multiplexers to pass write data from the MBIST logic to the ECC encoder circuitry and to pass address and control signals from the MBIST logic to respective ones of the physical module multiplexers, and configuring the MBIST logic to receive read data from the logical memory;
- based on the selection of the functional operation test, configuring the logical module multiplexers to pass write data from a converter, configured to perform reversible data transformations, to the ECC encoder circuitry and to pass address and control signals from the MBIST logic to respective ones of the physical module multiplexers, and configuring the MBIST logic and the converter to receive read data from the logical memory;
- and
- based on the selection of the non-test mode, configuring the logical module multiplexers to pass write data from functional logic to the ECC encoder circuitry and to pass address and control signals from the functional logic to respective ones of the physical module multiplexers, and configuring the functional logic to receive read data from the logical memory.
3 more elements
Dependencies are inferred from the claim text.