Semiconductor integrated circuit including a memory macro
AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
InventorKenichi Anzou
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Abstract
In general, according to one embodiment, there is provided a semiconductor integrated circuit including a memory macro. The memory macro includes a first ECC circuit that generates a code corresponding to input data, a memory core including a data storage portion on which reading and writing of data is performed, and an ECC storage portion on which reading and writing of a code is performed, a second ECC circuit that executes, based on data and code read from the memory core, error detection or correction of the data, and circuits that form a path in which data flows to bypass the memory core in a scan test, and form a path in which data flows through each of the data storage portion and the ECC storage portion in a memory test.
Claims11
A semiconductor integrated circuit comprising a memory macro including:
- a first error correction code (ECC) circuit that generates an error detection and correction code corresponding to input data;
- a memory core including a data storage portion on which reading and writing of data is performed, and an ECC storage portion on which reading and writing of a code is performed;
- a second ECC circuit that performs error detection or correction of data to be read from the data storage portion, using a code to be read from the ECC storage portion;
- a first path in which data flows from the first ECC circuit through each of the data storage portion and the ECC storage portion to the second ECC circuit in a memory test;
- and
- a second path in which data flows, from the first ECC circuit to the second ECC circuit, to bypass the memory core in a scan test.
Dependencies are inferred from the claim text.