Multi-port register file device and method of operation in normal mode and test mode

An operation processing device comprising:

• a storage unit;
• and
• an operation unit connected to the storage unit,
• wherein the storage unit includes:
• a first latch circuit configured to hold a plurality of sets of write addresses and write enable signals;
• a first disabling circuit, including inverters, AND circuits, and logical disjunction OR circuits, and configured to output the write enable signals without change when at least two write addresses of a plurality of write addresses for which write enable signals are enabled and held by the first latch circuit do not match;
• a second latch circuit configured to hold sets of the plurality of write addresses held by the first latch circuit and the plurality of write enable signals output by the first disabling circuit;
• a second disabling circuit, including inverters, AND circuits, and logical disjunction OR circuits, and configured to output one write enable signal of the plurality of write enable signals held by the second latch circuit without change and disable other write enable signals of the plurality of write enable signals held by the second latch circuit to output the disabled signals or configured to disable all the write enable signals to output the disabled signals, in accordance with mask data, in a test mode, the second disabling circuit being configured to output the plurality of write enable signals held by the second latch circuit without change in a normal mode;
• and
• a third latch circuit configured to write, in accordance with sets of the plurality of write addresses held by the second latch circuit and the plurality of write addresses output by the second disabling circuit, write data,
• wherein, in the test mode, the first latch circuit and the second latch circuit are mutually connected and test data is written in the first latch circuit and the second latch circuit.

A control method of a storage device, the method comprising:

• holding, by a first latch circuit included in the storage device, a plurality of sets of write addresses and write enable signals;
• outputting, by a first disabling circuit included in the storage device and including inverters, AND circuits, and logical disjunction OR circuits, the write enable signals without change when at least two write addresses of a plurality of write addresses for which write enable signals are enabled and held by the first latch circuit do not match;
• holding, by a second latch circuit included in the storage device, sets of the plurality of write addresses held by the first latch circuit and the plurality of write enable signals output by the first disabling circuit;
• outputting, by a second disabling circuit included in the storage device and including inverters, AND circuits, and logical disjunction OR circuits, one write enable signal of the plurality of write enable signals held by the second latch circuit without change and disabling other write enable signals of the plurality of write enable signals held by the second latch circuit to output the disabled signals or disabling all the write enable signals to output the disabled signals, in accordance with mask data, in a test mode;
• outputting, by the second disabling circuit included in the storage device, the plurality of write enable signals held by the second latch circuit without change in a normal mode;
• and
• writing, by a third latch circuit included in the storage device, in accordance with sets of the plurality of write addresses held by the second latch circuit and the plurality of write addresses output by the second disabling circuit, write data,
• wherein, in the test mode, the first latch circuit and the second latch circuit are mutually connected and test data is written in the first latch circuit and the second latch circuit.