Multi-level memory safety of a sensor integrated circuit
AssigneeAllegro MicroSystems, LLC
InventorsNicolas Rafael Biberidis, Octavio H. Alpago, Nicolas Rigoni
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Abstract
A method for multi-level memory safety for a sensor integrated circuit can include loading a blocking bit into a volatile memory from a non-volatile memory and providing the blocking bit to a gating circuit from the volatile memory. Further, the method may include the gating circuit determining whether to provide a default value to a functional logic based upon the provided blocking bit.
Claims32
A method for multi-level memory safety for a sensor integrated circuit, comprising:
- loading, from a non-volatile memory, a blocking bit into a volatile memory;
- providing, from the volatile memory, the blocking bit to a gating circuit;
- and
- determining, via the gating circuit, whether to provide a default value to a functional logic based upon the provided blocking bit.
A multi-level memory safety system for a sensor integrated circuit, comprising:
- a non-volatile memory coupled to a volatile memory and configured to load a blocking bit into the volatile memory;
- and
- a gating circuit coupled to the volatile memory and configured to receive the blocking bit from the volatile memory;
- wherein the gating circuit is further configured to output a default value according to the received blocking bit.
A multi-level memory safety system for a sensor integrated circuit, comprising:
- means for loading a blocking bit from a non-volatile memory into a volatile memory when the sensor integrated circuit is powered on;
- means for determining whether loading the blocking bit into the volatile memory was successful;
- and
- means for providing a default value to a functional logic according to the loaded blocking bit.
Dependencies are inferred from the claim text.