Memory system

A memory system comprising:

• a semiconductor memory that includes a memory cell array which stores data, an input/output circuit through which the data is output, a first data latch circuit which temporally holds the data after the data is read from the memory cell array, and a second data latch circuit between the first data latch circuit and the input/output circuit;
• and
• a controller configured to perform operations on the semiconductor memory including a read operation,
• wherein, during the read operation in which read data is read from the memory cell array into the first data latch circuit and then transferred to the second data latch circuit, the controller transmits a command for instructing data transmission from the second data latch circuit to the controller, to the semiconductor memory before completion of the read data transfer is from the first data latch circuit to the second data latch circuit.

A method of performing a read operation in a semiconductor memory device including a memory cell array, an input/output circuit, a first data latch configured to latch data read from the memory cell array, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, said method comprising:

• sensing data stored in the memory cell array and latching the sensed data in the first data latch;
• transferring the data latched in the first data latch to the second data latch;
• outputting a ready/busy signal having a busy state while the data stored in the memory cell array is sensed and latched and during a first period of the transferring;
• and
• start outputting the ready/busy signal having a ready state before completion of the transferring of the data latched in the first data latch to the second data latch.