Asymmetric pass field-effect transistor for non-volatile memory
AssigneeLongitude Flash Memory Solutions Ltd.
InventorsSungkwon Lee, Venkatraman Prabhakar
Life of this patent
Estimating the term…
Abstract
A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.
Claims15
A memory device comprising:
- a first non-volatile memory (NVM) device including a single or a plurality of first memory transistors and a first pass transistor at one side of the memory device and a second pass transistor at the other side, wherein the single or the plurality of first memory transistors, the first pass transistor, and the second pass transistor of the first NVM device are connected together in series;
- a second non-volatile memory (NVM) device including a single or a plurality of second memory transistors and a first pass transistor at one side of the memory device and a second pass transistor at the other side, wherein the single or the plurality of second memory transistors, the first pass transistor, and the second pass transistor of the second NVM device are connected together in series;
- a common source line (CSL) coupled with at least a source of one of the first and second pass transistors of each of the first NVM device and the second NVM device, wherein at least one of the first and second pass transistors of each of the first NVM device and the second NVM device is an asymmetric transistor;
- wherein the operation of each NVM device of the first NVM device and the second NVM device includes:
- applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the corresponding NVM device;
- and
- applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the corresponding NVM device.
The memory device of claim , wherein the source or the drain of at least one of the first and second pass transistors of at least one of the first NVM device and the second NVM device includes no implant doped region.
Dependencies are inferred from the claim text.