System and method for avoiding back to back program failure
AssigneeWestern Digital Technologies, Inc.
InventorsRohit Sehgal, Grishma Shah, Sahil Sharma, Phil Reusswig
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AssigneeWestern Digital Technologies, Inc.
InventorsRohit Sehgal, Grishma Shah, Sahil Sharma, Phil Reusswig
Estimating the term…
In one embodiment, there is a system comprising a first group of blocks connected to a first address line, a second group of blocks connected to a second address line separate and distinct from the first address line, a host controller (or memory device) configured to: allocate a single open block to each of: the first group of blocks connected to the first address line that transmits an address signal generated by a first peripheral circuitry module, and the second group of blocks connected to the second address line that transmits an address signal generated by a second peripheral circuitry module; in response to receiving a first program request: program the open block in the first group of blocks connected to the first address line in response to a first program request in response to receiving a second program request separate and distinct from the first program request: forego programming any of the blocks in the first group of blocks connected to the first address line; and program one of the blocks in the second group of blocks connected to the second address line.
A system comprising:
A method for minimizing back-to-back program failures at a storage system including a first group of blocks connected to a first address line, a second group of blocks connected to a second address line separate and distinct from the first address line, and a memory device configured to perform the steps of:
A storage system including a first group of blocks connected to a first address line, a second group of blocks connected to a second address line separate and distinct from the first address line, and a memory device comprising:
Dependencies are inferred from the claim text.