Failure detection circuitry for address decoder for a data storage device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHidehiro Fujiwara, Ching-Wei Wu
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Abstract
A data storage device can detect for a failure in decoding of an x-bit row address and/or a y-bit column of an (x+y)-bit address. The data storage device decodes the x-bit row address and/or the y-bit column address to provide wordlines (WLs) and/or bitlines (BLs) to access one or more cells from among a memory array of the data storage device. The data storage device compares one or more subsets of the WLs and/or of the BLs to each other to detect for the failure. The data storage device determines the failure is present in the decoding of the x-bit row address and/or the y-bit column of the (x+y)-bit address when one or more WL and/or BL from among the one or more subsets of the WLs and/or the BLs differ.
Claims20
A data storage device, comprising:
- a memory array including a plurality of memory cells, the memory array being logically grouped into a first memory sub-array and a second memory sub-array, respectively, from among a plurality of memory sub-arrays;
- and
- a column decoder configured to:
- decode a column address within an address to access a memory cell from among the plurality of memory cells to provide a plurality of bitlines (BLs) corresponding to the column address, a first BL and a second BL from among the plurality of BLs being associated with the first memory sub-array and the second memory sub-array, respectively, and
- indicate a failure in the decoding of the column address when the first BL differs from the second BL.
A method for operating a data storage device having a memory array including a plurality of memory cells that are logically grouped into a plurality of memory sub-arrays, the method comprising:
- decoding a column address within an address to access a memory cell from among a plurality of memory cells to provide a plurality of bitlines (BLs) corresponding to the column address, a first BL and a second BL from among the plurality of BLs being associated with the first memory sub-array and the second memory sub-array, respectively, from among the plurality of memory sub-arrays;
- and
- indicating a failure in the decoding of the column address when the first BL differs from the second BL.
A column decoder for decoding a column address within an address to access a memory cell from among a plurality of memory cells in a memory array to provide a plurality of bitlines (BLs) corresponding to the column address, the memory array being logically grouped into a first memory sub-array and a second memory sub-array, respectively, from among a plurality of memory sub-arrays, the column decoder comprising:
- a first parallel address decoder and a second parallel address decoder from among a plurality of parallel address decoders configured to decode the column address to provide a first BL and a second BL from among the plurality of BLs, respectively, the first parallel address decoder and the second parallel address decoder corresponding to the first memory sub-array and the second memory sub-array, respectively;
- and
- failure detection circuitry configured to:
- charge a failure indication line to approximately a charging voltage,
- compare the first BL and the second BL,
- sample the failure indication line at one or more instances in time, and
- provide a first logical value to indicate the failure in the decoding of the column address when the sampled failure indication line is at approximately the charging voltage.
Dependencies are inferred from the claim text.