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US 10,706,932 B2Granted
Memory device and operating method thereof
AssigneeSK hynix Inc.
InventorsEun Kyu In, Jae Woo Park, Seok Won Park, Byung Ryul Kim
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Abstract
A memory device prevents generation of an abnormal column address. The memory device includes: a memory cell array; and a column address controller configured to generate a column address of the memory cell array in response to a column address control signal, wherein the column address controller enables the column address control signal when an address signal is input, and wherein the address signal includes a column address signal corresponding to the column address.
Claims18
A memory device comprising:
- a memory cell array;
- and
- a column address controller configured to enable a column address control signal in response to an address signal and generate a column address of the memory cell array in response to the column address control signal,
- wherein the address signal, including a column address signal corresponding to the column address, is input during a plurality of cycles of a reference clock of the memory device,
- wherein the column address signal is input during at least two cycles among the plurality of cycles, and
- wherein the column address control signal is disabled in at least one of the at least two cycles.
3 more elements
A memory device comprising:
- a memory cell array;
- and
- a control logic configured to receive a command signal instructing performance of an operation on selected memory cells among the plurality of memory cells from an external controller and an address signal indicating positions of the selected memory cells,
- wherein the control logic includes a column address controller configured to enable a column address control signal in response to the address signal and generate a column address of the memory cell array in response to the column address control signal, which corresponds to a column address signal included in the address signal,
- wherein the address signal including the column address signal corresponding to the column address, is input during a plurality of cycles of a reference clock of the memory device,
- wherein the column address signal is input during at least two cycles among the plurality of cycles, and
- wherein the column address control signal is disabled in the at least one of the at least two cycles.
4 more elements
Dependencies are inferred from the claim text.