Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorHiroshi Maejima
Life of this patent
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Abstract
A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
Claims15
A semiconductor memory device, comprising:
- a memory cell array having a plurality of memory strings spaced from each other in a first direction, each memory string having a first selection transistor, a second selection transistor, and a plurality of memory cells connected in series between the first selection transistor and second selection transistor;
- a plurality of word lines that are each connected to a gate of a memory cell in a memory string in the plurality of memory strings, the plurality of word lines spaced from each other in a second direction which intersects the first direction;
- a plurality of bit lines that are each connected to first selection transistors of the memory strings;
- a plurality of first selection gate lines that are each connected to gates of the first selection transistors;
- a plurality of second selection gate lines that are each connected to gates of the second selection transistors;
- a source line that is connected to each of the second selection transistors;
- and
- a controller configured to, during a read operation:
- apply a first voltage to the first selection gate lines during a first period of the read operation, the first voltage being sufficient to turn on the first selection transistors,
- apply a second voltage to each of the first selection gate lines connected to non-selected memory strings during a second period of the read operation after the first period, the second voltage being higher than a ground voltage and lower than the first voltage, and
- apply a third voltage to each of the second selection gate lines connected to selected memory strings during the second period, the third voltage being higher than a ground voltage and lower than the first voltage.
A semiconductor memory device, comprising:
- a controller configured to cause data stored in a first memory cell of a first memory string in a memory cell array to be read by performing a read operation, the read operation including:
- in a first period, applying a first voltage to a first selection gate line connected to a gate of a first selection transistor of the first memory stirring and to a second selection gate line connected to a gate of a second selection transistor of the first memory string,
- in a second period after the first period, applying a second voltage to the first selection gate line and the second selection gate line to turn on the first selection transistor and a third selection transistor of a second memory string, the second voltage being higher than the first voltage, and
- in a third period after the second period, applying a third voltage to the second selection gate line to turn off the third selection transistor, while maintaining the second voltage applied to the first selection gate line, the third voltage being higher than the first voltage and lower than the second voltage.
Dependencies are inferred from the claim text.