Non-volatile memory device, in particular phase change memory, and reading method

A method for reading a memory cell of a non-volatile memory device having a memory array formed by a plurality of memory cells arranged in rows and columns, wherein at least one first memory cell storing a datum is arranged in a first column and is coupleable to a first bit line;

• a first circuit branch is associated to the first bit line and has a first node coupled to the first bit line, an output node, and a current source controllable to inject a shift current in the first bit line, the shift current having a value higher than a current passing the first memory cell when the first memory cell is in a first programming state, and lower than the current passing the first memory cell when the first memory cell is in a second programming state,
• the method comprising:
• a precharging step, wherein the first memory cell is disabled, the first bit line is precharged at a line precharging voltage, and the current source is deactivated and does not supply the shift current;
• a characteristic shift step, wherein the first memory cell is enabled and connected to the first bit line, the first bit line is decoupled from the output node, and the current source supplies the shift current to the first bit line, and wherein, on the basis of the datum stored, the bit line goes to a shifted voltage, lower or higher than the precharging line voltage;
• and
• a detection step, wherein the shift current is interrupted, the first bit line is connected to the output node, and the translated voltage is compared with a reference voltage.

A non-volatile memory device, comprising:

• a memory array formed by a plurality of memory cells arranged in rows and columns, wherein at least one first memory cell storing a datum is arranged in a first column and is coupleable to a first bit line;
• a first circuit branch associated to the first bit line and having:
• a first node coupled to the first bit line;
• an output node;
• and
• a switch configured to selectively couple the first node to the first memory cell and the first bit line to the output node;
• a comparator stage having a first input coupled to the output node, a second input coupled to a reference voltage, and an output supplying an output signal indicative of a datum stored in the first memory cell;
• a current source, controllable to inject a shift current into the first bit line, the shift current having a value higher than a current passing in the first memory cell when the latter is in a first programming state, and lower than the current passing in the first memory cell when the latter is in a second programming state;
• and
• a control unit configured to control the switch.