Semiconductor memory device

A semiconductor memory device comprising:

• a first memory cell;
• a second memory cell;
• a first bit line pair that is coupled to the first memory cell;
• a second bit line pair that is coupled to the second memory cell and disposed to run parallel to the first bit line pair;
• a write driver circuit;
• a write assist circuit;
• and
• a select circuit,
• wherein, in accordance with a select signal, when the select circuit couples the first bit line pair to the write driver circuit and couples the second bit line pair to the write assist circuit:
• the write driver circuit causes one bit line of the first bit line pair to transition from a high level to the a low level in accordance with input data;
• and
• the write assist circuit causes one bit line of the second bit line pair to transition from a high level to a low level, the one bit line of the second bit line pair being disposed in association with the one bit line of the first bit line pair, the one bit line of the first bit line pair being placed at the low level,
• wherein, when the one bit line of the second bit line pair is transitioned from the high level to the low level, the one bit line transitioned to the low level is placed in a high-impedance state, and
• wherein the one bit line of the first bit line pair transitions from the low level to a negative potential in accordance with the transition of the one bit line of the second bit line pair from the high level to the low level.

A semiconductor memory device comprising:

• a first memory cell and a second memory cell that each includes a first port and a second port;
• a first bit line pair that is coupled to the first port of the first memory cell;
• a second bit line pair that is coupled to the first port of the second memory cell and disposed to run parallel to the first bit line pair;
• a third bit line pair that is coupled to the second port of the first memory cell;
• a fourth bit line pair that is coupled to the second port of the second memory cell and disposed to run parallel to the third bit line pair;
• a first write circuit;
• and
• a first select circuit,
• wherein the first write circuit includes:
• a write driver circuit;
• and
• a write assist circuit, and
• wherein, in accordance with a select signal, when the first select circuit couples the first bit line pair to the write driver circuit of the first write circuit and couples the second bit line pair to the write assist circuit of the first write circuit,
• wherein the semiconductor memory device further includes:
• a second write circuit;
• and
• a second select circuit,
• wherein the second write circuit includes:
• a write driver circuit;
• and
• a write assist circuit,
• wherein, in accordance with the select signal, when the second select circuit couples the third bit line pair to the write driver circuit of the second write circuit and couples the fourth bit line pair to the write assist circuit of the second write circuit,
• wherein the write driver circuit of the first write circuit causes one bit line of the first bit line pair to transition from a high level to a low level in accordance with input data, and
• wherein the write assist circuit of the first write circuit causes one bit line of the second bit line pair to transition from a high level to a low level, the one bit line of the second bit line pair being disposed in association with the one bit line of the first bit line pair, the one bit line of the first bit line pair being placed at the low level,
• wherein, when the one bit line of the second bit line pair is transitioned from the high level to the low level, the one bit line transitioned to the low level is placed in a high-impedance state, and
• wherein the one bit line of the first bit line pair transitions from the low level to a negative potential in accordance with the transition of the one bit line of the second bit line pair from the high level to the low level.