Method and circuit for adaptive read-write operation in self-timed memory

A method, comprising:

• performing a dummy operation to a column of dummy memory cells controlled by a second dummy word line portion, the performing of the dummy operation including:
• generating a first word line voltage on a first dummy word line portion coupled to the second dummy word line portion by a voltage drop circuit;
• generating a second word line voltage on the second dummy word line portion, with the second word line voltage being less than the first word line voltage due to current flow from the first dummy word line portion, across the voltage drop circuit, to the second dummy word line portion;
• and
• reading from or writing to the column of dummy memory cells, and asserting a flag when the read or write is completed.

A method comprising:

• performing a dummy operation to a column of dummy memory cells controlled by a second dummy word line portion, the performing of the dummy operation including:
• generating a first word line voltage on a first dummy word line portion;
• generating a second word line voltage on the second dummy word line portion, with the second word line voltage being less than the first word line voltage, wherein the second word line voltage is generated by coupling the first and second dummy word line portions together with a transmission gate, and connecting a voltage divider between the second dummy word line portion and ground;
• and
• reading from or writing to the column of dummy memory cells, and asserting a flag when the read or write is completed.

A method, comprising:

• performing a dummy operation to a column of dummy memory cells controlled by a second dummy word line portion, the performing of the dummy operation including:
• generating a first word line voltage on a first dummy word line portion;
• generating a second word line voltage on the second dummy word line portion, with the second word line voltage being less than the first word line voltage;
• and
• reading from or writing to the column of dummy memory cells, and asserting a flag when the read or write is completed;
• generating an internal clock signal that has a first transition at an edge of an external clock and second transition at assertion of the flag, the second transition being a next transition of the internal clock signal after the first transition;
• and
• performing a read cycle or write cycle on some of an array of memory cells that begins at the first transition of the internal clock signal and ends at the second transition of the internal clock signal.