Static random access memory
AssigneeUnited Microelectronics Corp.
InventorsChun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Hsin-Chih Yu, Shu-Ru Wang
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Abstract
A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.
Claims7
A static random access memory (SRAM) structure, comprising:
- a four-transistors SRAM (4T-SRAM), wherein the 4T-SRAM comprises a first pass transistor, a second pass transistor, a first drive transistor and a second drive transistor;
- the first pass transistor comprising a first source/drain terminal coupled to a first storage node;
- the second pass transistor comprising a second source/drain terminal coupled to a second storage node;
- the first drive transistor comprising a third source/drain terminal coupled to the first storage node;
- the second drive transistor comprising a fourth source/drain terminal coupled to the second storage node;
- a first magnetic tunnel junction (MTJ) structure coupled to the first storage node, wherein the first MTJ structure does not comprise a gate;
- and
- a second magnetic tunnel junction (MTJ) structure coupled to the second storage node, wherein the second MTJ structure does not comprise a gate, wherein the first MTJ structure is coupled between the first storage node and a Vss voltage source, and the second MTJ structure is coupled between the second storage node and the Vss voltage source.
Dependencies are inferred from the claim text.