Reduced transport energy in a memory system
AssigneeRambus Inc.
InventorsFrederick A. Ware, John Eric Linstadt, Thomas Vogelsang
Life of this patent
Estimating the term…
Abstract
A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.
Claims20
A memory stack comprising:
- an array of memory elements comprising a first memory element coupled to a bit line, the first memory element to operate at a first voltage level;
- a first column line coupled to the bit line of the first memory element, wherein a signal on the first column line is at the first voltage level;
- a first data link;
- a first voltage reduction circuit coupled between the first column line and the first data link, the first voltage reduction circuit to reduce the first voltage level of the signal to a second voltage level before being transmitted via the first data link;
- and
- a first voltage amplification circuit coupled to the first data link, the first voltage amplification circuit to increase the second voltage level of the signal to a third voltage level after being transmitted via the first data link.
A memory device comprising:
- an array of memory elements comprising a first memory element coupled to a bit line, the first memory element to operate at a first voltage level;
- a first column line coupled to the bit line of the first memory element, wherein a signal on the first column line is at the first voltage level;
- a first data link;
- a first voltage reduction circuit coupled between the first column line and the first data link, the first voltage reduction circuit to reduce the first voltage level of the signal to a second voltage level before being transmitted via the first data link;
- and
- a first voltage amplification circuit coupled to the first data link, the first voltage amplification circuit to increase the second voltage level of the signal to a third voltage level after being transmitted via the first data link.
A memory device comprising:
- an array of memory elements comprising a first memory element configured to operate at a first voltage level, wherein a signal from the first memory element is at the first voltage level;
- a first internal data link;
- and
- a voltage reduction circuit coupled to the first internal data link, the voltage reduction circuit to reduce the first voltage level of the signal to a second voltage level before being transmitted via the first internal data link, wherein the voltage reduction circuit comprises:
- a pair of logic gates controlled by an enable signal, the pair of logic gates to receive the signal from the first memory element as a first differential signal;
- and
- two sets of transistor stacks, wherein the pair of logic gates drive the two sets of transistor stacks to provide a second differential signal at the second voltage level when enabled by the enable signal.
Dependencies are inferred from the claim text.