Memories configured to control discharge of a control gate voltage of a transistor connected between a data line and a common source

A memory, comprising:

• a plurality of strings of series-connected memory cells;
• a plurality of data lines, wherein each data line of the plurality of data lines is selectively connected to a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;
• a common source selectively connected to the plurality of strings of series-connected memory cells;
• and
• control logic configured to perform an erase operation on the plurality of strings of series-connected memory cells, wherein, during the erase operation, the control logic is further configured to cause the memory to:
• apply a first particular voltage level to a first voltage node capacitively coupled to a voltage level of a particular data line of the plurality of data lines, then allow the first voltage node to electrically float;
• apply a second particular voltage level to a second voltage node capacitively coupled to the voltage level of the particular data line, then allow the second voltage node to electrically float;
• concurrently discharge the voltage level of the particular data line and a voltage level of a common source while the particular data line is connected to the common source through a transistor;
• compare a voltage level of the first voltage node to a voltage level of a third voltage node capacitively coupled to a voltage level of a control gate of the transistor;
• compare a voltage level of the second voltage node to a voltage level of a fourth voltage node capacitively coupled to the voltage level of the control gate of the transistor;
• activate a current path between the control gate of the transistor and the common source while the voltage level of the third voltage node is deemed to be greater than the voltage level of the first voltage node;
• and
• deactivate the current path between the control gate of the transistor and the common source while the voltage level of the fourth voltage node is deemed to be less than the voltage level of the second voltage node.

A memory, comprising:

• a plurality of strings of series-connected memory cells;
• a plurality of data lines, wherein each data line of the plurality of data lines is selectively connected to a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;
• a common source selectively connected to the plurality of strings of series-connected memory cells;
• a plurality of first transistors, wherein each first transistor of the plurality of first transistors is connected between a respective data line of the plurality of data lines and the common source;
• a plurality of second transistors, wherein each second transistor of the plurality of second transistors is connected between a control gate of a respective first transistor of the plurality of first transistors and the common source;
• and
• control logic configured to perform an erase operation on the plurality of strings of series-connected memory cells, wherein, during the erase operation, the control logic is further configured to cause the memory to:
• apply an erase pulse having a first voltage level to each data line of the plurality of data lines and to the common source concurrently with applying a second voltage level, higher than the first voltage level, to the control gate of each first transistor of the plurality of first transistors;
• after applying the erase pulse, concurrently discharge the voltage level of each data line of the plurality of data lines and the voltage level of the common source;
• and
• for each data line of the plurality of data lines:
• monitor a representation of a respective voltage difference between the voltage level of that data line and the voltage level of the control gate of the respective first transistor for that data line;
• activate the respective second transistor for the respective first transistor for that data line in response to the respective voltage difference for that data line being deemed to be greater than a first value that is less than a breakdown voltage of the respective first transistor for that data line, and greater than a threshold voltage of the respective first transistor for that data line;
• and
• deactivate the respective second transistor for the respective first transistor for that data line in response to the respective voltage difference for that data line being deemed to be less than a second value that is greater than the threshold voltage of the respective first transistor for that data line, and less than the breakdown voltage of the respective first transistor for that data line.