Sense amplifier for sensing multi-level cell and memory device including the sense amplifier
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-Hun Seo, Kyung-Ryun Kim
Life of this patent
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Abstract
A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.
Claims20
A sense amplifier, comprising:
- a first sense amplification circuit electrically connected between a bit line, to which a memory cell is also connected, and a complementary bit line, said first sense amplification circuit configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB of the 2-bit data in a first sensing bit line pair;
- a second sense amplification circuit configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB of the 2-bit data in a second sensing bit line pair;
- and
- a switching circuit configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.
A method of sensing multi-bit memory cell data, comprising:
- sensing a most significant bit (MSB) of 2-bit data and latching the MSB of the 2-bit data into a first sensing bit line pair, using a first charge sharing operation occurring between a charge stored in a memory cell and charge stored on a bit line;
- and
- sensing a least significant bit (LSB) of the 2-bit data and latching the LSB of the 2-bit data into a second sensing bit line pair, using a second charge sharing operation, which comprises sharing charge between a charge stored in the bit line and a charge stored in the first complementary sensing bit line, and sharing charge between a charge stored in a complementary bit line and a charge stored in a first sensing bit line.
A memory device comprising:
- a memory cell storing a cell voltage represented as multi-bit data in a 2-bit combination;
- and
- a sense amplifier connected between a bit line, to which the memory cell is connected, and a complementary bit line, and configured to sense the cell voltage as most significant bit (MSB) data and least significant bit (LSB) data in the 2-bit combination,
- wherein the sense amplifier comprises:
- a first sense amplification circuit configured to sense the LSB data to latch the LSB data in a first sensing bit line pair;
- a second sense amplification circuit configured to sense MSB data in the 2-bit combination to latch the MSB data in a second sensing bit line pair;
- and
- a switching circuit configured to selectively connect between bit lines of the first sensing bit line pair and between bit lines of the second sensing bit line pair.
Dependencies are inferred from the claim text.