Memory controller
AssigneeRambus Inc.
InventorsFrederick A. Ware, Ely K. Tsern, Richard E. Perego, Craig E. Hampel
Life of this patent
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Abstract
A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.
Claims20
A memory controller component comprising:
- a clock driver to transmit a first clock signal to a dynamic random access memory device (DRAM), the DRAM having read-data transmit circuitry to output read data at transmit times dependent on transitions of the first clock signal and write-data receive circuitry to sample write data at sampling times dependent on transitions of the first clock signal;
- a write-data transmitter to transmit the write data to the DRAM in response to transitions of a second clock signal;
- a read-data receiver to sample the read data transmitted by the DRAM in response to transitions of a third clock signal;
- and
- clocking circuitry to generate the second and third clock signals in response to transitions of the first clock signal, the clocking circuitry including phase control circuitry to independently offset phases of the second and third clock signals relative to the first clock signal.
A method of operation within a memory controller component, the method comprising:
- outputting a first clock signal to a dynamic random access memory device (DRAM), the DRAM having read-data transmit circuitry to output read data at transmit times dependent on transitions of the first clock signal and write-data receive circuitry to sample write data at sampling times dependent on transitions of the first clock signal;
- transmitting write data to the DRAM in response to transitions of a second clock signal;
- sampling read data transmitted by the DRAM in response to transitions of a third clock signal;
- and
- generating the second and third clock signals in response to transitions of the first clock signal, including independently offsetting phases of the second and third clock signals relative to the first clock signal.
A memory controller component comprising:
- means for outputting a first clock signal to a dynamic random access memory device (DRAM), the DRAM having read-data transmit circuitry to output read data at transmit times dependent on transitions of the first clock signal and write-data receive circuitry to sample write data at sampling times dependent on transitions of the first clock signal;
- means for transmitting write data to the DRAM in response to transitions of a second clock signal;
- means for sampling read data transmitted by the DRAM in response to transitions of a third clock signal;
- and
- means for generating the second and third clock signals in response to transitions of the first clock signal, including means for independently offsetting phases of the second and third clock signals relative to the first clock signal.
Dependencies are inferred from the claim text.