Refresh control circuit, semiconductor memory device, and refresh method thereof

A refresh control circuit, comprising:

• a plurality of fuse circuits each including a plurality of fuse sets for programming repair addresses of a corresponding memory bank among a plurality of memory banks;
• a plurality of counting units suitable for generating a plurality of count values by counting the number of fuse sets that are used in each fuse circuit;
• a counting detection unit suitable for detecting a maximum value among the count values and outputting a detection signal;
• an address generation circuit suitable for sequentially generating redundant addresses for selecting redundant word lines based on a refresh signal, and initializing the redundant addresses based on a redundant reset signal;
• and
• a reset signal generation unit suitable for generating the redundant reset signal based on the detection signal and the redundant address.

A method for refreshing a semiconductor memory device, comprising:

• providing first to Nth memory banks and first to Nth non-volatile memories each including a plurality of memory sets for programming repair addresses of the corresponding memory banks;
• generating first to Nth count values by counting a number of the memory sets used in the first to Nth non-volatile memories;
• generating a redundant reset signal based on a maximum value among the first to Nth count values;
• generating normal addresses for selecting normal word lines, which sequentially increase by counting a refresh signal;
• and
• generating redundant addresses for selecting redundant word lines by counting the refresh signal after the normal addresses reach the maximum value based on a refresh signal, and initializing the redundant addresses based on the redundant reset signal.

A semiconductor memory device, comprising:

• a plurality of memory banks, each including a normal cell region coupled to normal word lines and a redundant cell region coupled to redundant word lines;
• a plurality of non-volatile memories, each of the plurality of non-volatile memory corresponding to each of the plurality of memory banks and including a plurality of repair addresses for the redundant cell region;
• a refresh control circuit suitable for generating a redundant reset signal by counting a number of the repair address;
• and
• a refresh circuit suitable for generating normal addresses for selecting the normal word lines, which sequentially increase by counting a refresh signal, generating redundant addresses for selecting the redundant word lines by counting the refresh signal after the normal addresses reach the maximum value, and initializing the redundant addresses based on the redundant reset signal.