Dynamic reference scheme for improving read margin of resistive memory array
AssigneesNational University of Singapore, Agency Fpr Science, Technology and Research
InventorsKien Trinh Quang, Massimo Alioto, Sergio Ruocco
Life of this patent
Estimating the term…
Abstract
A method of providing a reference voltage for reading of a resistive memory array, and a read circuit for reading of a resistive memory array. The method comprises the steps of generating a first reference voltage when a bitline of the resistive memory array is in a first resistance state, and generating a second reference voltage when the bitline is in a second resistance state; wherein the first reference voltage is different from the first reference voltage and the first resistance state is different from the second resistance state.
Claims16
A method of providing a reference voltage for reading of a resistive memory array, the method comprising the steps of:
- generating a first reference voltage when a bitline of the resistive memory array is in a first resistance state, and
- generating a second reference voltage when the bitline is in a second resistance state;
- wherein the first reference voltage is different from the first reference voltage and the first resistance state is different from the second resistance state;
- wherein generating the first and second reference voltages comprises applying a gain to a voltage of the bitline;
- and
- wherein the gain is chosen such that a bit error rate for reading in the first resistance state of the bitline is substantially the same as a bit error rate for reading in the second resistance state.
A read circuit for reading of a resistive memory array, the circuit comprising:
- a reference voltage generating circuit for generating a first reference voltage when a bitline of the resistive memory array is in a first resistance state, and for generating a second reference voltage when the bitline is in a second resistance state, wherein the first reference voltage is different from the first reference voltage and the first resistance state is different from the second resistance state;
- wherein the reference voltage generating circuit applies a gain to a voltage of the bitline in generating the first and second reference voltages;
- and
- wherein the gain is chosen such that a bit error rate for reading in the first resistance state of the bitline is substantially the same as a bit error rate for reading in the second resistance state.
Dependencies are inferred from the claim text.