Interconnections for 3D memory
AssigneeMicron Technology, Inc.
InventorToru Tanzawa
Life of this patent
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Abstract
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.
Claims20
An apparatus, comprising:
- a vertical string of memory cells coupled to a data line;
- a plurality of access lines coupled to the memory cells and control circuitry;
- and
- a switchable conductive path arranged between the plurality of access lines,
- wherein the plurality of access lines are coupled to the control circuitry through interconnections formed of a same material as the plurality of access lines, the interconnections located in a plane parallel to planes in which the plurality of access lines are formed and having a longest dimension in a direction different from a direction of a longest dimension of the plurality of access lines.
An apparatus, comprising:
- a memory array including a plurality of access lines;
- a switchable conductive path arranged between the plurality of access lines;
- and
- a controller coupled to the memory array, wherein the controller is configured to cause:
- a first voltage level to be applied to a selected one of the access lines;
- a second voltage level to be provided a non-selected one of the access lines;
- and
- the selected one of the access lines and the non-selected one of the access lines to have a substantially equal voltage after performance of a memory operation.
A method, comprising:
- performing a memory operation on a three dimensional memory array including a string of memory cells and access lines coupled to the string and to control circuitry through interconnections located in a plane parallel to planes in which the plurality of access lines are formed and having a longest dimension in a direction different from a direction of a longest dimension of the plurality of access lines by
- providing a first voltage level to a selected one of the access lines;
- providing a second voltage level to a non-selected one of the access lines, the second voltage level being higher than the first voltage level;
- and
- after performing the memory operation, controlling the selected one of the access lines and the non-selected one of the access lines to have a substantially equal voltage.
Dependencies are inferred from the claim text.