Display device
AssigneeAu Optronics Corporation
InventorsChen-Yang Wei, Hsiang-Pin Fan, Wen-Hao Hsu
Life of this patent
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Abstract
A display device includes a plurality of pixels, a plurality of gate lines, a timing controller, and a gate driver. The gate lines are electrically coupled to the pixels. The timing controller provides an initial pulse signal. The gate driver is electrically coupled to the timing controller and the gate lines and receives the initial pulse signal. The gate driver receives the initial pulse signal with a high level and outputs a plurality of gate signals to the gate lines during a period which is longer than half of a frame of the display device, in response to a scan frequency of the display device changing from a first frequency to a second frequency, where the first frequency is higher than the second frequency.
Claims7
A display device, comprising:
- a plurality of pixels;
- a plurality of gate lines, electrically coupled to the plurality of pixels;
- a timing controller, configured to provide an initial pulse signal;
- and
- a gate driver, electrically coupled to the timing controller and the plurality of gate lines, and configured to receive the initial pulse signal, wherein the timing controller is configured to provide the initial pulse signal with a first enable width when a scan frequency of the display device is a first frequency and further configured to provide the initial pulse signal with a second enable width when the scan frequency of the display device is a second frequency, the first frequency is higher than the second frequency, the second enable width is larger than the first enable width, and the gate driver is further configured to output a plurality of gate signals to the plurality of gate lines in response to the initial pulse signal,
- wherein the gate driver comprises a driving circuitry configured to receive a clock signal, and to output the clock signal to one of the plurality of gate lines as one of the plurality of gate signals in response to the initial pulse signal with a high level;
- and
- wherein the clock signal has a first pulse during the first enable width of the initial pulse signal for the first frequency, the clock signal has second pulses during the second enable width of the initial pulse signal for the second frequency, and a length of time of the second pulses of the clock signal during the second enable width of the initial pulse signal for the second frequency is longer than a length of time of the first pulse of the clock signal during the first enable width of the initial pulse signal for the first frequency.
Dependencies are inferred from the claim text.