Gate driver and organic light emitting display device including the same

A gate driver including a plurality of stages dependently connected to each other, each stage comprising:

• a first output unit which outputs a sensing signal in accordance with voltages of a Q node and a QB node;
• a second output unit which outputs a reference signal in accordance with the voltages of the Q node and the QB node;
• a third output unit which outputs a scan signal in accordance with the voltages of the Q node and the QB node;
• a first controller which controls the Q node;
• and
• a second controller which controls the QB node,
• wherein at least two of the first to third output units share at least one clock signal among a plurality of clock signals,
• wherein the second output unit and the third output unit are supplied with first clock signals having different phases from each other and the first output unit is supplied with a second clock signal,
• wherein the second output unit is supplied with an (n−1) th phase first clock signal and the third output unit is supplied with an (n) th phase first clock signal,
• wherein the first output unit includes a first pull-up TFT which outputs the second clock signal as the sensing signal in accordance with the voltage of the Q node and a first pull-down TFT which outputs the low potential voltage as the sensing signal in accordance with the voltage of the QB node,
• the second output unit includes a second pull-up TFT which outputs the (n−1) th phase first clock signal as the reference signal in accordance with the voltage of the Q node and a second pull-down TFT which outputs the low potential voltage as the reference signal in accordance with the voltage of the QB node, and
• the third output unit includes a third pull-up TFT which outputs the (n) th phase first clock signal as the scan signal in accordance with the voltage of the Q node and a third pull-down TFT which outputs the low potential driving voltage as the scan signal in accordance with the voltage of the QB node.

A gate driver including a plurality of stages dependently connected to each other, each stage comprising:

• a first output unit which outputs a sensing signal in accordance with voltages of a Q node and a QB node;
• a second output unit which outputs a reference signal in accordance with the voltages of the Q node and the QB node;
• a third output unit which outputs a scan signal in accordance with the voltages of the Q node and the QB node;
• a first controller which controls the Q node;
• and
• a second controller which controls the QB node,
• wherein at least two of the first to third output units share at least one clock signal among a plurality of clock signals,
• wherein the first controller includes:
• a first QTFT which outputs a high potential driving voltage to the Q node in accordance with a carry signal of a previous stage;
• and
• a second QTFT which outputs a low potential driving voltage to the Q node in accordance with a carry signal of a subsequent stage,
• wherein the second controller includes an inverter in which the Q node is connected to an input terminal and the QB node is connected to an output terminal.

An organic light emitting display device, comprising:

• a display panel including a plurality of pixels;
• and
• a gate driver which is mounted in the display panel, shares at least one clock signal among a plurality of clock signals and outputs a sensing signal, a reference signal, and a scan signal
• wherein the gate driver includes a plurality of stages which is dependently connected to each other, and
• each of the plurality of stages includes:
• a first output unit which outputs the sensing signal in accordance with voltages of a Q node and a QB node;
• a second output unit which outputs the reference signal in accordance with the voltages of the Q node and the QB node;
• a third output unit which outputs the scan signal in accordance with the voltages of the Q node and the QB node;
• a first controller which controls the Q node;
• and
• a second controller which controls the QB node, wherein at least two of the first to third output units share at least one clock signal among a plurality of clock signals and
• wherein the first output unit includes a first pull-up TFT which outputs a second clock signal as the sensing signal in accordance with the voltage of the Q node and a first pull-down TFT which outputs a low potential voltage as the sensing signal in accordance with the voltage of the QB node,
• wherein the second output unit includes a second pull-up TFT which outputs a (n−1) th phase first clock signal as the reference signal in accordance with the voltage of the Q node and a second pull-down TFT which outputs the low potential voltage as the reference signal in accordance with the voltage of the QB node, and
• wherein the third output unit includes a third pull-up TFT which outputs a (n) th phase first clock signal as the scan signal in accordance with the voltage of the Q node and a third pull-down TFT which outputs the low potential driving voltage as the scan signal in accordance with the voltage of the QB node.

An organic light emitting display device, comprising:

• a display panel including a plurality of pixels;
• and
• a gate driver which is mounted in the display panel, shares at least one clock signal among a plurality of clock signals and outputs a sensing signal, a reference signal, and a scan signal,
• wherein a pixel circuit disposed in the plurality of pixels includes:
• a driving TFT which controls a current flowing in an organic light emitting diode based on voltages which are applied to a gate node and a source node of the driving TFT;
• a first switching TFT which applies an initialization voltage to the source node of the driving TFT based on the sensing signal;
• a second switching TFT which applies a reference voltage to the gate node of the driving TFT based on the reference signal;
• a third switching TFT which applies a data voltage to the gate node of the driving TFT based on the scan signal;
• and
• a fourth switching TFT which applies a high potential voltage to a drain node of the driving TFT based on an emission control signal.

An organic light emitting display device, comprising:

• a display panel including a plurality of pixels;
• and
• a gate driver which is mounted in the display panel, shares at least one clock signal among a plurality of clock signals and outputs a sensing signal, a reference signal, and a scan signal,
• wherein the gate driver includes a plurality of stages which is dependently connected to each other, and each of the plurality of stages includes:
• a first output unit which outputs the sensing signal in accordance with voltages of a Q node and a QB node;
• a second output unit which outputs the reference signal in accordance with the voltages of the Q node and the QB node;
• a third output unit which outputs the scan signal in accordance with the voltages of the Q node and the QB node;
• a first controller which controls the Q node;
• and
• a second controller which controls the QB node,
• wherein at least two of the first to third output units share at least one clock signal among a plurality of clock signals,
• wherein the first output unit and the third output unit are supplied with first clock signals having different phases from each other and the second output unit is supplied with a second clock signal,
• wherein the first output unit is supplied with an (n−2) th phase first clock signal and the third output unit is supplied with an (n) th phase first clock signal,
• wherein the first output unit includes a first pull-up TFT which outputs the (n−2) th phase first clock signal as the sensing signal in accordance with the voltage of the Q node and a first pull-down TFT which outputs a low potential voltage as the sensing signal in accordance with the voltage of the QB node,
• wherein the second output unit includes a second pull-up TFT which outputs the second clock signal as the reference signal in accordance with the voltage of the Q node and a second pull-down TFT which outputs the low potential voltage as the reference signal in accordance with the voltage of the QB node, and
• wherein the third output unit includes a third pull-up TFT which outputs the (n) th phase first clock signal as the scan signal in accordance with the voltage of the Q node and a third pull-down TFT which outputs the low potential driving voltage as the scan signal in accordance with the voltage of the QB node.