Shift register unit circuit, driving method thereof, gate drive circuit and display device

A method of driving a shift register unit circuit, the shift register unit circuit comprising:

• an input circuit configured to supply an active potential from a first scan level terminal to a first node in response to an input pulse from an input terminal being active, and to supply an inactive potential from a second scan level terminal to the first node in response to a reset pulse from a reset terminal being active, an output circuit configured to supply a first clock signal from a first clock terminal to an output terminal in response to a second node being at the active potential, and to cause a potential at the second node to be changed from the active potential to further away from the inactive potential in response to a potential at the output terminal transitioning from the inactive potential to the active potential;
• and a potential control circuit configured to restrict a change in a potential at the first node caused by the transition of the potential at the output terminal from the inactive potential to the active potential, wherein the first node is directly connected to the second node, and wherein the potential control circuit comprises a second capacitor connected between the second node and a first reference level terminal for supplying the inactive potential:
• wherein the potential control circuit is further configured to supply an active potential from a second reference level terminal to the second scan level terminal in response to the output terminal being at the active potential;
• and wherein the potential control circuit further comprises a control transistor having a gate connected to the output terminal, a first electrode connected to the second reference level the method comprising:
• responsive to the input pulse from the input terminal being active, supplying the active potential from the first scan level terminal to the first node;
• responsive to the second node being at the active potential, supplying the first clock signal from the first clock terminal to the output terminal;
• responsive to the output terminal transitioning from being at the inactive potential to being at the active potential, causing the potential at the second node to be changed from the active potential to further away from the inactive potential;
• restricting a change in the potential at the first node caused by the transition of the potential at the output terminal from the inactive potential to the active potential;
• and responsive to the reset pulse from the reset terminal being active, supplying the inactive potential from the second scan level terminal to the first node.