Shift register, method for driving the same, gate driver circuit, and display device

A shift register, comprising:

• an input circuit configured to provide a first node with a signal of an input signal terminal under the control of the input signal terminal;
• a reset circuit configured to provide the first node with a signal of a reference voltage signal terminal under the control of a reset signal terminal;
• a first control circuit configured to control a level at the first node, and a level at a second node;
• a first output circuit configured to provide a drive signal output terminal of the shift register with a signal of a first clock signal terminal under the joint control of the signal of the first clock signal terminal and a signal of the first node, and to provide the drive signal output terminal with a signal of a second clock signal terminal under the joint control of the signal of the second clock signal terminal and the signal of the first node, wherein the signal of the first clock signal terminal and the signal of the second clock signal terminal have a same cycle, and opposite phases;
• and
• a second output circuit configured to provide the drive signal output terminal with the signal of the reference voltage signal terminal respectively under the control of the signal of the input signal terminal and a signal of the second node,
• wherein the first output circuit comprises a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, and a storage capacitor, wherein:
• the first switch transistor has a control electrode connected with the first node, a first electrode connected with the first clock signal terminal, and a second electrode connected with a control electrode of the second switch transistor;
• the second switch transistor has a first electrode connected with the first clock signal terminal, and a second electrode connected with the drive signal output terminal;
• the third switch transistor has a control electrode connected with the first node, a first electrode connected with the second clock signal terminal, and a second electrode connected with a control electrode of the fourth switch transistor;
• the fourth switch transistor has a first electrode connected with the second clock signal terminal, and a second electrode connected with the drive signal output terminal;
• and
• the storage capacitor is connected between the first node and the drive signal output terminal.