Integrated circuit

An integrated circuit, comprising:

• a data storage circuit, a weight storage circuit and an operation circuit;
• the data storage circuit and the weight storage circuit electrically connected to the operation circuit;
• the data storage circuit configured to store gray-scale value data of an image in a first preset time period, according to a preset control instruction, the weight storage circuit configured to store a data weight corresponding to the gray-scale value data of the image in the first preset time period, the operation circuit configured to carry out an operation on the gray-scale value data in the data storage circuit and the data weight in the weight storage circuit in the first preset time period, and output first data;
• the data storage circuit further configured to store the first data in a second preset time period, according to the preset control instruction, the weight storage circuit further configured to store the data weight corresponding to the first data in the second preset time period, and the operation circuit further configured to carry out an operation on the first data in the data storage circuit and the data weight corresponding to the first data and stored in the weight storage circuit, and output second data wherein the data storage circuit comprises:
• a data memory, N*M−1 selectors, N*M data registers, and N−1 First in First Output (FIFO) memories;
• a first switch selection port of each selector and an input port of a first data register electrically connected to a data output port of the data memory, second switch selection ports of first to (M−1)-th selectors correspondingly and electrically connected to positive phase output ports of first to (M−1)-th data registers respectively, and a second switch selection port of a M-th selector electrically connected to an output port of a first FIFO memory, a positive phase output port of a M-th data register electrically connected to an input port of the first FIFO memory;
• a second switch selection port of each of ((N−2)*M+1)-th to ((N−1)*M−1)-th selectors respectively and electrically connected to a positive phase output port of each of ((N−2)*M+1)-th to ((N−1)*M−1)-th data registers correspondingly, a second switch selection port of a (N−1)*M-th selector correspondingly and electrically connected to an output port of a (N−1)-th FIFO memory, and a positive phase output port of a (N−1)*M-th data register correspondingly and electrically connected to an input port of the (N−1)-th FIFO memory;
• second switch selection ports of ((N−1)*M+1)-th to (N*M−1)-th selectors respectively and electrically connected to positive phase output ports of ((N−1)*M+1)-th to (N*M−1)-th data registers correspondingly, output ports of first to (N*M−1)-th selectors correspondingly and electrically connected to input ports of second to N*M-th data registers respectively, and positive phase output ports of first to N*M-th data registers electrically connected to the operation circuit;
• the N*M data registers configured to receive the gray-scale value data of the image transmitted by the data memory in the first preset time period, and receive the data in the first data transmitted by the data memory in the second preset time period;
• the N*M−1 selectors configured to make the second switch selection port of each selector electrically connected to the positive phase output port of each data register or the output port of each FIFO memory, and make the first switch selection port of each selector disconnected from the data output port of the data memory in the first preset time period, and make the first switch selection port of each selector electrically connected to the data output port of the data memory, and make the second switch selection port of each selector disconnected from the positive phase output port of each data register or the output port of each FIFO memory in the second preset time period, according to the preset control instruction;
• wherein, M and N are positive integers greater than 1.