Estimation of effective channel length for FinFETs and nano-wires
AssigneeSynopsys, Inc.
InventorsVictor Moroz, Yong-Seog Oh, Stephen Lee Smith, Michael C. Shaughnessy-Culver, Jie Liu
Life of this patent
Estimating the term…
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AssigneeSynopsys, Inc.
InventorsVictor Moroz, Yong-Seog Oh, Stephen Lee Smith, Michael C. Shaughnessy-Culver, Jie Liu
Estimating the term…
Roughly described, a system for estimating an effective channel length of a 3D transistor having a gate length below 20 nm involves estimating an effective volume of the channel and a cross-sectional area of the channel, and estimating the effective channel length as the ratio of effective volume to cross-sectional area. Preferably the effective volume is estimated as the sum of the Voronoi volumes within containing boundaries of the channel, excluding those volumes having a dopant concentration above the source/drain dopant concentration at the carrier injection point. The containing boundaries can be identified using geometry data describing the transistor, particularly the data identifying inner surfaces of the gate dielectric. The estimated effective channel length can be used in TCAD level analysis of the transistor and calculating characteristics of the transistor as needed for circuit simulation.
A system for enhancing simulations of three-dimensional transistors, the system comprising:
A method for enhancing simulations of three-dimensional transistors, comprising the steps of:
A non-transitory computer readable medium having stored thereon a plurality of software code portions defining logic for enhancing simulations of three-dimensional transistors, the software code portions defining logic for:
A system for enhancing simulations of three-dimensional transistors, for use with a computer system having accessibly thereto a data set describing a dopant profile of a three-dimensional transistor having a semiconductor body, the data set also identifying a gate length for the three-dimensional transistor which is no greater than 20 nm, the data set further identifying surfaces of gate dielectric material adjacent to the semiconductor body, the data set further describing source/drain dopant concentration within each of a plurality of sub-volumes within the semiconductor body, the system comprising:
Dependencies are inferred from the claim text.