Priority aware balancing of memory usage between geometry operation and file storage

In an electronic design automation (EDA) toolset implemented by a processor of a computing system, a layout verification tool configured to verify a layout description of a circuit design using a geometry engine configured to perform a plurality of geometric operations, the computing system including main memory resources that are directly coupled to the processor and storage memory resources that are indirectly coupled to the processor, wherein the geometry engine is configured such that each said geometric operation includes processing one or more previously-generated geometric operation data files and generating a corresponding current geometric operation data file, said layout verification tool including instructions that, when executed by said processor, cause the processor to perform a method comprising:

• before performing a current geometric operation of said plurality of geometric operations, determining an estimated minimum amount by which currently available memory of said main memory resources must be increased to perform said current geometric operation, said current available memory capacity being defined by a difference between a total capacity amount of said main memory resources and an unavailable portion of said total capacity amount occupied by one or more previously generated geometric operation data files;
• selecting at least one data file from said one or more previously generated geometric operation data files, said at least one data file being selected such that a difference between an amount of said unavailable portion occupied by said at least one data file and said estimated minimum amount is minimized;
• transferring said at least one selected data file from said main memory resources to said storage memory resources, whereby said current available memory amount of said main memory resources is increased by said amount of said unavailable portion occupied by said at least one data file;
• and
• performing said current geometric operation.

An apparatus, comprising:

• a processor;
• and a non-transitory computer-readable storage medium storing instructions that, when executed by the processor, cause the processor to perform a method for managing memory resources during a layout verification process, the processor being directly coupled to main memory resources and indirectly coupled to storage memory resources, said layout verification process being configured to verify a layout description by performing a plurality of geometric operations, where each said geometric operation includes processing one or more previously-generated geometric operation data files and generating a corresponding current geometric operation data file, said method comprising:
• before performing a current geometric operation of said plurality of geometric operations, determining an estimated minimum amount by which currently available memory of said main memory resources must be increased to perform said current geometric operation, said current available memory capacity being defined by a difference between a total capacity amount of said main memory resources and an unavailable portion of said total capacity amount occupied by one or more previously generated geometric operation data files;
• selecting at least one data file from said one or more previously generated geometric operation data files, said at least one data file being selected such that a difference between an amount of said unavailable portion occupied by said at least one data file and said estimated minimum amount is minimized;
• transferring said at least one selected data file from said main memory resources to said storage memory resources, whereby said current available memory amount of said main memory resources is increased by said amount of said unavailable portion occupied by said at least one data file;
• and
• performing said current geometric operation.