US 10,706,207 B2 · Circuit design verification apparatus and program

Abstract

A program embodied in a non-transitory computer readable medium includes instructions executable by a processor to perform a method of verifying a circuit design. The method includes the steps of performing an automated analysis of the circuit design by scanning an assertion description file and a signal list file of the circuit design, creating and displaying a scheme based on the assertion description file, wherein the scheme includes nodes and arcs, the nodes indicating output signals and the arcs indicating a transition relationship between nodes, and identifying in the scheme assertions that are missing from the assertion description, and recommending amendments to the assertion description to supply the missing assertions, the missing assertions, when added, being reflected in the display of the scheme.

Claims18

Dependent claims

A circuit design verification apparatus, comprising:

a processor;
and
a memory coupled to the processor and storing a program that when executed by the processor causes the processor to:
scan an assertion description file of a circuit design and a signal list file of the circuit design,
based on the assertion description file and the signal list file, generate and display a graph including nodes corresponding to output signals and arcs corresponding to a transition relationship between nodes, and
use the graph to identify assertions that are missing from the assertion description file, and generate recommended amendments to the assertion description file to supply the missing assertions, wherein
a missing assertion is identified by the processor by detecting a node in the graph having no arcs connected thereto.

4 more elements

Dependencies are inferred from the claim text.

Circuit design verification apparatus and program

Life of this patent

Circuit design verification apparatus and program

Life of this patent

Abstract

Claims18