US 10,706,195 B1 · System, method, and computer program product for over-constraint/deadcode detection in a formal verification

Abstract

The present disclosure relates to a method for use in the formal verification of an electronic circuit. Embodiments may include receiving, using a processor, a portion of an electronic circuit design and analyzing a syntactic structure of a string associated with the electronic circuit design. Embodiments may also include generating a parse tree, based upon, at least in part, the analysis and traversing the parse tree to identify one or more conditional nodes. Embodiments may further include generating a new node for each of the one or more conditional nodes and displaying, at a graphical user interface, a check, at least one of the one or more conditional nodes or the new node prior to performing either register-transfer-level RTL synthesis or final synthesis.

Claims20

Dependent claims

A computer-implemented method comprising:

receiving, using a processor, a portion of an electronic circuit design;
analyzing a syntactic structure of a string associated with the electronic circuit design;
generating a parse tree, based upon, at least in part, the analysis;
traversing the parse tree to identify one or more conditional nodes;
generating a new node for each of the one or more conditional nodes;
and
displaying, at a graphical user interface, an option to define or select a check associated with at least one of the one or more conditional nodes or the new node prior to performing either register-transfer-level RTL synthesis or final synthesis.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/989,469Filed 25 May 2018

Granted

7 Jul 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking
G06F 30/30
Computer-aided design [CAD]: circuit design
G06F 30/31
Circuit design: design entry, e.g. editors specifically adapted for circuit design
G06F 30/367
Circuit design at the analogue level: design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE],…

System, method, and computer program product for over-constraint/deadcode detection in a formal verification

Life of this patent

System, method, and computer program product for over-constraint/deadcode detection in a formal verification

Life of this patent

Abstract

Claims20