Voltage reconciliation in multi-level power managed systems

In an electronic Design Automation (EDA) tool implemented on a computer, a method for verifying a multi-level power managed system description before the production of an integrated circuit device based on said system description, wherein said system description includes a top-level circuit description and one or more lower-level circuit descriptions, wherein said top level circuit description includes a top-level Unified Power Format (UPF) design file including first power states utilized by said top-level circuit description, and wherein each of said one or more lower-level circuit descriptions includes a corresponding lower-level UPF design file identifying second power states utilized by said each lower-level circuit description, said method comprising:

• utilizing said initial top-level UPF design file and said initial lower-level UPF design files to generate a plurality of original Power State Table (PSTs), said plurality of original PSTs including an original lower-level PST Upper PST for each of said one or more lower-level circuit descriptions, and an original top-level PST for said top-level circuit description, said one or more original PSTs including a plurality of power state entries, each said power state entry including an associated set of voltage level values generated by associated said power supplies during a corresponding said power state, wherein each said voltage level value includes one of an on-state voltage level value and an off-state indicator value;
• generating initial supply relationships for each said original PST, wherein each said initial supply relationship includes either a higher/lower voltage level relationship for each associated pair of said on-state voltage level values or an on-off transition relationship that is determined by stored voltage levels of two power supplies included in an associated said original PST;
• generating reconciled PSTs by revising stored voltage values for each power supply in each original PST using a primary voltage value that is established for said each power supply, said primary voltage value being defined by a main driver of said each power supply;
• generating final supply relationships for each said reconciled PST, wherein each said final supply relationship includes either a higher/lower voltage level relationship or an on-off transition relationship that is determined by revised voltage levels of two power supplies included in an associated said reconciled PST;
• and
• verifying that each initial supply relationship has a matching final supply relationship and that each final supply relationship has a matching initial supply relationship by comparing said initial supply relationships and said final supply relationships.