Apparatus and method for chip identification and preventing malicious manipulation of physical addresses by incorporating a physical network with a logical network

A semiconductor device comprising:

• a semiconductor chip including a cell array, with the cell array having a group of row lines and a group of column lines, with the group of row lines and the group of column lines intersect and form cross-points;
• wherein the cell array includes a plurality of identification cells distributed at the cross-points;
• wherein each row line in the group of row lines is respectively assigned with a row number and each column line in the group of column lines is respectively assigned with a column number;
• wherein the cell array is divided into a plurality of sub-blocks, with each of the plurality of sub-blocks respectively includes a portion of the plurality of identification cells;
• wherein each of the plurality of identification cells has a cell address defined by a set of the row number and the column number of the cross-point at which the identification cell is located;
• wherein each of the plurality of sub-blocks has a block address defined by sets of the row numbers and the column numbers of the cross-points encompassed in the sub-block;
• wherein the cell address is related to the block address and an inner address of a sub-block, with the inner address related to the block address;
• wherein a portion of the block addresses includes at least one of the cell addresses at which an identification cell exhibiting a predetermined characteristic is located, with the predetermined characteristic based on a physical randomness which is intrinsic of the semiconductor chip;
• and wherein the semiconductor chip further has a physical random number code including the portion of the block address, with the physical random number code being secured by the semiconductor chip,
• each of the plurality of identification cells respectively comprises a resistor cell having a resistance with a measurable resistivity, a conductor cell having a conductance with a measurable conductivity, a capacitor having a dielectric or a ferroelectric with a measurable permittivity sandwiched between conductive components, and an element selected from a PN junction, a Schottky junction, a transistor, and a nonvolatile memory cell including a charge storage layer,
• wherein each of the plurality of identification cells respectively comprises a combination of the transistor and the capacitor having the ferroelectric with the measurable permittivity sandwiched between the conductive components.

A semiconductor device comprising:

• a semiconductor chip including a cell array, with the cell array having a group of row lines and a group of column lines, with the group of row lines and the group of column lines intersect and form cross-points;
• wherein the cell array includes a plurality of identification cells distributed at the cross-points;
• wherein each row line in the group of row lines is respectively assigned with a row number and each column line in the group of column lines is respectively assigned with a column number;
• wherein the cell array is divided into a plurality of sub-blocks, with each of the plurality of sub-blocks respectively includes a portion of the plurality of identification cells;
• wherein each of the plurality of identification cells has a cell address defined by a set of the row number and the column number of the cross-point at which the identification cell is located;
• wherein each of the plurality of sub-blocks has a block address defined by sets of the row numbers and the column numbers of the cross-points encompassed in the sub-block;
• wherein the cell address is related to the block address and an inner address of a sub-block, with the inner address related to the block address;
• wherein a portion of the block addresses includes at least one of the cell addresses at which an identification cell exhibiting a predetermined characteristic is located, with the predetermined characteristic based on a physical randomness which is intrinsic of the semiconductor chip;
• and wherein the semiconductor chip further has a physical random number code including the portion of the block address, with the physical random number code being secured by the semiconductor chip,
• wherein a fail bit is assigned to a cell address at which an identification cell exhibiting a characteristic with a deviation more than a predetermined range is located, wherein the sub-block is a fail sub-block if the sub-block includes the cell address assigned with the fail bit, and the sub-block is a regular sub-block if the sub-block does not include the cell address assigned with the fail bit, with the cell array comprising a plurality of fail sub-blocks and a plurality of regular sub-blocks.