Dynamically updating logical identifiers of cores of a processor

A system comprising:

• a processor having:
• a plurality of cores, each of the plurality of cores including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core;
• a power controller, based at least in part on a temperature associated with a first core, to dynamically remap a first logical identifier from association with the first core to association with a second core while the first core and the second core are in a low power state, to cause a first thread in execution on the first core to be migrated from the first core to the second core transparently to an operating system;
• a first mapping table including a plurality of entries each to store a logical identifier-to-physical identifier association for a core;
• an input/output (I/O) interface to couple to one or more devices and to provide an incoming message to a selected core;
• and
• a second mapping table coupled to the I/O interface including a second plurality of entries each to store a logical identifier-to-physical identifier association for a core, wherein the power controller is to dynamically update a first entry of the first mapping table to associate the first logical identifier with the second core and cause a dynamic update to a corresponding entry of the second mapping table to associate the first logical identifier with the second core;
• and
• a system memory coupled to the processor, wherein the system memory comprises a non-volatile storage.

A processor comprising:

• a plurality of cores, each of the plurality of cores including a first storage to store a physical identifier for the core and a second storage separate from the first storage to store a logical identifier associated with the core, the physical identifier for the core not visible to an operating system;
• a plurality of thermal sensors to measure a temperature at a corresponding location of the processor;
• a plurality of power sensors to measure a power at a corresponding location of the processor;
• a plurality of wear sensors to measure wear information regarding the plurality of cores;
• a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on at least one of a temperature and a power associated with the first core, the dynamic remapping to cause a first thread in execution on the first core to be migrated from the first core to the second core;
• and
• a mapping table including a plurality of entries each to store a logical identifier-to-physical identifier association, wherein the dynamic core identifier logic is to update an entry of the mapping table associated with the second core in response to the dynamic remapping of the first logical identifier to the second core to store the first logical identifier in the entry associated with the second core.