Back to results
US 10,706,003 B2Granted
Reduced pin count interface
AssigneeIntel Corporation
InventorsMichelle Jen, Daniel Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
Life of this patent
Estimating the term…
Abstract
An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.
Claims25
An apparatus comprising:
- media access layer (MAC) circuitry;
- and
- an interface to couple to a device comprising physical layer (PHY) circuitry, wherein the interface comprises a PHY Interface for a Peripheral Component Interconnect (PCI) Express architecture (PIPE)-based interface and comprises:
- a set of transmit pins to transmit data to the PHY circuitry;
- a set of receive pins to receive data from the PHY circuitry;
- and
- a set of pins to implement a message bus interface,
- wherein the MAC circuitry is to access a set of message bus registers associated with the PHY circuitry via the message bus interface, respective bits in the set of message bus registers represent a plurality of control and status signals, a particular bit in the set of message bus registers represents a particular signal in the plurality of control and status signals, and the MAC circuitry is to write a value to the particular bit to initiate an operation associated with the particular signal.
5 more elements
An apparatus comprising:
- physical layer (PHY) circuitry;
- and
- a Peripheral Component Interconnect (PCI) Express architecture (PIPE)-based interface to couple to a device comprising media access layer (MAC) circuitry, wherein the PIPE interface comprises a message bus interface comprising:
- a set of transmit pins to send commands to access a first message bus register associated with the MAC circuitry, wherein bits in the first message bus register represent a first set of signals;
- and
- a set of receive pins to receive commands to allow the MAC circuitry to access a second message bus register associated with the PHY circuitry, wherein bits in the second message bus register represent a second set of signals,
- wherein the PHY circuitry is to write values to the first message bus register to access functionality associated with the first set of signals, the PHY circuitry is to initiate operations responsive to values written to the second message bus register by the MAC circuitry, and the operations correspond to the second set of signals.
4 more elements
A system comprising:
- a first device comprising physical layer (PHY) circuitry and a first set of message bus registers, wherein the first set of message bus registers comprise first bits to represent a first set of signals,
- a second device comprising media access layer (MAC) circuitry and a second set of message bus registers, wherein the second set of message bus registers comprise second bits to represent a second set of signals;
- and
- an interface to couple the first device to the second device, wherein the interface comprises:
- a first set of lanes to transmit first data from the second device to the first device;
- a second set of lanes to transmit second data from the first device to the second device;
- and
- a message bus interface comprising a third set of lanes to enable access to the second set of message bus registers and a fourth set of lanes to enable access to the first set of message bus registers,
- wherein the first device is to send commands on the third set of lanes to the second device to write to the bits in the second set of registers to initiate operations associated with the second set of signals, and the second device is to send commands on the fourth set of lanes to the first device to write to the bits in the first set of registers to initiate operations associated with the first set of signals.
6 more elements
Dependencies are inferred from the claim text.