Exchange of data between processor modules

A method of operating a processing system comprising an arrangement of multiple processor modules and at least a first interconnect for exchanging data between different sets of the processor modules, each processor module comprising a respective execution unit for executing a program and respective memory for storing the program and data operated on by the program, and each set comprising one or more of the processor modules;

• the method comprising:
• arranging a group of some or all of the processor modules to operate in a series of bulk synchronous parallel, BSP, supersteps, whereby in each superstep, each processor module in the group performs a compute phase in which it performs computations but does not exchange results of the computations outside its own set, and a preceding exchange phase to exchange the results of one or more computations with one or more others of the processor modules in one or more others of the sets via said first interconnect, the group being synchronized by a barrier synchronization between each current superstep in the series and the next whereby each processor module in the group waits for all in the group to complete the compute phase of the current superstep before advancing to the exchange phase of the next superstep;
• for the exchange phase of each superstep, pre-programming each receiving processor module that is to receive a number of units of data from outside its own set is with a respective value representing said number of units of data, and arranging each receiving processor module, starting from the pre-programmed value, to count out the number of units of data remaining to be received each time one of said units of data is received;
• and
• arranging each receiving processor module to perform an exchange synchronization whereby, before advancing from the exchange phase to the compute phase of the current superstep, the receiving processor module waits until no units of data remain to be received according to said count.

A computer program product embodied on computer readable storage and comprising a respective program for running on each of multiple processor modules, using at least a first interconnect for exchanging data between different sets of the processor modules, each processor module comprising a respective execution unit for executing the respective program and respective memory for storing the respective program and data operated on the respective program, and each set comprising one or more of the processor modules;

• the computer program product being configured so as when run on the multiple processor modules to perform operations of:
• controlling a group of some or all of the processor modules to operate in a series of bulk synchronous parallel, BSP, supersteps, whereby in each superstep, each processor module in the group performs a compute phase in which it performs computations but does not exchange results of the computations outside its own set, and a preceding exchange phase to exchange the results of one or more computations with one or more others of the processor modules in one or more others of the sets via said first interconnect, the group being synchronized by a barrier synchronization between each current superstep in the series and the next whereby each processor module in the group waits for all in the group to complete the compute phase of the current superstep before advancing to the exchange phase of the next superstep;
• for the exchange phase of each superstep, setting each receiving processor module that is to receive a number of units of data from outside its own set is with a respective value representing said number of units of data, and controlling each receiving processor module, starting from the pre-programmed value, to count out the number of units of data remaining to be received each time one of said units of data is received;
• and
• controlling each receiving processor module to perform an exchange synchronization whereby, before advancing from the exchange phase to the compute phase of the current superstep, the receiving processor module waits until no units of data remain to be received according to said count.