US 10,705,994 B2 · Unified cache for diverse memory traffic

Abstract

A unified cache subsystem includes a data memory configured as both a shared memory and a local cache memory. The unified cache subsystem processes different types of memory transactions using different data pathways. To process memory transactions that target shared memory, the unified cache subsystem includes a direct pathway to the data memory. To process memory transactions that do not target shared memory, the unified cache subsystem includes a tag processing pipeline configured to identify cache hits and cache misses. When the tag processing pipeline identifies a cache hit for a given memory transaction, the transaction is rerouted to the direct pathway to data memory. When the tag processing pipeline identifies a cache miss for a given memory transaction, the transaction is pushed into a first-in first-out (FIFO) until miss data is returned from external memory. The tag processing pipeline is also configured to process texture-oriented memory transactions.

Claims20

Dependent claims

A memory subsystem, comprising:

a first memory;
a first data pathway that services first-type memory transactions and provides direct access to the first memory;
and
a second data pathway that services second-type memory transactions of a first sub-type and second-type memory transactions of a second sub-type and includes:
a first data sub-pathway that is coupled to the first data pathway and transports second-type memory transactions of the first sub-type to the first data pathway when a first condition occurs, and
a second data sub-pathway that is coupled to the first memory and services second-type memory transactions of the second sub-type.

3 more elements

A computer-implemented method for servicing memory transactions, the method comprising:

receiving a first memory transaction;
determining a type associated with the first memory transaction;
when the first memory transaction has a first type, routing the first memory transaction across a first data pathway that provides direct access to a first memory;
and
when the first memory transaction has a second type:
routing the first memory transaction across a second data pathway that includes a first data sub-pathway and a second data sub-pathway,
determining a sub-type associated with the first memory transaction, and
routing the first memory transaction across one of the first data sub-pathway and the second data sub-pathway based on the sub-type.

5 more elements

Dependencies are inferred from the claim text.

Unified cache for diverse memory traffic

Life of this patent

Unified cache for diverse memory traffic

Life of this patent

Abstract

Claims20