Autonomous prefetch engine

A memory device, comprising

• system level cache (SLC);
• and
• control circuitry comprising:
• a circuit configured to identify memory access requests received at the system level cache (SLC) from a system on a chip (SoC) component, wherein each of the memory access requests include an address (ANEXT) of memory to be accessed and a component ID;
• a circuit configured to associate a tracker, from among a plurality of trackers, with each of identified memory access streams,
• wherein each of the plurality of trackers comprise entry parameters of status, increment, address distance (ADIST), age (AGE), temporal distance (TDIST), prefetch status (PF), current address (ACURR), and last prefetched address (ALAST);
• and
• a circuit configured to perform tracking for each of the identified memory access streams by:
• when the status is tracking and the address (ANEXT) points to an interval between the current address (ACURR) and the last prefetched address (ALAST), issuing a prefetch request to the system level cache (SLC);
• and
• when the status is tracking, and distance (ADIST) between the current address (ACURR) and the last prefetched address (ALAST) is greater than a specified maximum prefetch for the associated tracker, waiting for further requests to control a prefetch process.

A method for controlling memory prefetch requests to system level cache (SLC), the method comprising:

• identifying memory access requests received at the system level cache (SLC) from a system on a chip (SoC) component, wherein each of the memory access requests include an address (ANEXT) of memory to be accessed and a component ID;
• associating a tracker, from among a plurality of trackers, with each of identified memory access streams, wherein each of the plurality of trackers comprise entry parameters of status, increment, address distance (ADIST), age (AGE), temporal distance (TDIST), prefetch status (PF), current address (ACURR), and last prefetched address (ALAST);
• issuing a prefetch request to the system level cache (SLC), when the status is tracking and the address (ANEXT) points to an interval between the current address (ACURR) and the last prefetched address (ALAST);
• and
• waiting for further requests to control a prefetch process, when the status is tracking, and distance (ADIST) between the current address (ACURR) and the last prefetched address (ALAST) is greater than a specified maximum prefetch for the associated tracker.