Scalable processor-assisted guest physical address translation
AssigneeIntel Corporation
InventorsRavi Sahita, Barry E. Huntley, Vedvyas Shanbhogue, Dror Caspi, Baruch Chaikin, Gilbert Neiger, Arie Aharon, Arumugam Thiyagarajah
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Abstract
Examples include a processor including at least one untrusted extended page table (EPT), circuitry to execute a set of instructions of the instruction set architecture (ISA) of the processor to manage at least one secure extended page table (SEPT), and a physical address translation component to translate a guest physical address of a guest physical memory to a host physical address of a host physical memory using one of the at least one untrusted EPT and the at least one SEPT.
Claims21
An apparatus comprising:
- a processor including
- instruction set architecture (ISA) circuitry to execute or more secure extended page table (SEPT) instructions to walk at least one SEPT stored in a protected area of a host physical memory that is inaccessible by an untrusted virtual machine manager (VMM);
- and
- physical address translation circuitry to translate a guest physical address of a guest physical memory to a host physical address of the host physical memory using the at least one SEPT.
A system, comprising:
- a host physical memory including a protected area that is inaccessible by an untrusted virtual machine manager (VMM) to store at least one secure extended page table (SEPT);
- a processor, coupled to the host physical memory, the processor including
- instruction set architecture (ISA) circuitry to execute one or more SEPT instructions to walk the at least one SEPT;
- and
- a physical address translation component to translate a guest physical address of a guest physical memory to a host physical address of the host physical memory using the SEPT.
A method comprising:
- receiving a request to translate a guest physical address of a guest physical memory to a host physical address of a host physical memory;
- determining if a shared bit of the guest physical address is set;
- and
- walking a secure extended page table (SEPT) to translate the guest physical address when the shared bit is not set, the SEPT being stored in a protected area of the host physical memory that is inaccessible by an untrusted virtual machine manager (VMM), the walking of the SEPT being performed by executing one or more SEPT instructions of an instruction set architecture (ISA) of a processor.
Dependencies are inferred from the claim text.