Dedupe DRAM cache

A dedupable cache, comprising:

• a cache memory, the cache memory including a dedupable read cache and a non-dedupable write buffer;
• a deduplication engine to manage data reads and writes using the dedupable read cache, the deduplication engine operative to send a write status signal indicating whether a write request to the dedupable read cache was successful or not;
• and
• a cache controller, including:
• a cache hit/miss check logic to check whether an address in a request may be found in the dedupable read cache;
• a hit block to access a first data from the cache memory when the cache hit/miss check logic indicates the address may be found in the dedupable read cache;
• a miss block to access a second data from a backend high capacity memory when the cache hit/miss check logic indicates the address may not be found in the dedupable read cache;
• and
• a history storage to store information about accesses to the first data in the dedupable read cache.