US 10,705,967 B2 · Programmable interface to in-memory cache processor

Abstract

The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

Claims21

Dependent claims

A processor, comprising:

memory circuitry that includes a plurality of static random access memory (SRAM) arrays;
processor circuitry to:
compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first programming language to an intermediate domain-specific language (DSL);
and
compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), wherein each of the multiple instruction sets corresponds to a respective layer of the multi-layer neural network model;
and
memory controller circuitry to:
configure multiple of the SRAM arrays within the plurality of SRAM arrays to operate as serially coupled, pipelined SRAM architecture (PISA) circuitry;
and
assign each of the multiple instruction sets to a respective one of the multiple SRAM arrays for execution by the respective one SRAM array.

7 more elements

A non-transitory machine-readable storage device having instructions that, when executed by processing circuitry, cause the processing circuitry to perform neural network processing operations comprising to:

receive, in a first programming language, data representative of a multi-layer neural network model and one or more neural network data inputs;
compile, via the processor circuitry, the data representative of the multi-layer neural network model and the one or more neural network data inputs from the first programming language to an intermediate domain-specific language (DSL);
compile, via the processor circuitry, the data representative of the multi-layer neural network model and the one or more neural network data inputs from the intermediate DSL to multiple instruction sets, each of the multiple instruction sets being in accordance with an instruction set architecture (ISA) and corresponding to a respective layer of the multi-layer neural network model;
configure, via the processor circuitry and memory circuitry that is coupled to the processor circuitry, multiple static random access memory (SRAM) arrays of a plurality of SRAM arrays within the memory circuitry to operate as serially coupled pipelined SRAM architecture (PISA) circuitry;
and
assign, via the processor circuitry, each of the multiple instruction sets to a respective one of the multiple SRAM arrays.

3 more elements

Dependencies are inferred from the claim text.

Programmable interface to in-memory cache processor

Life of this patent

Programmable interface to in-memory cache processor

Life of this patent

Abstract

Claims21