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US 10,705,963 B2Granted
Latency-based storage in a hybrid memory system
AssigneeMicron Technology, Inc.
InventorsDanilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato, Daniele Balluchi, Luca Porzio
Life of this patent
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Abstract
An example apparatus comprises a hybrid memory system and a controller coupled to the hybrid memory system. The controller may be configured to cause data to be selectively stored in the hybrid memory system responsive to a determination that an exception involving the data has occurred.
Claims21
A method, comprising:
- allocating a portion of a hybrid memory system comprising a flash memory device, a resistance variable memory device, and a controller for use in a code paging operation;
- determining that a fault exception corresponding to a read or write access request for a particular set of data associated with a main memory of a host coupleable to the hybrid memory system is going to occur;
- performing the code paging operation in response to determining that the host will experience the fault exception;
- and
- selectively transferring the particular set of data from the host to the allocated portion of the flash memory device or the phase change random access memory device of the hybrid memory system by mapping a logical block address (LBA) associated with the main memory of the host to the flash memory device or the resistance variable memory device that is configured to exhibit a lower write latency based, at least in part, on performance of the code paging operation and a determination that executing instructions to access a portion of the main memory in which the particular set of data is maintained will cause the fault exception to occur.
2 more elements
An apparatus, comprising:
- a hybrid memory system comprising a first non-volatile memory (NVM) resource, a second NVM resource, and a controller,
- wherein the controller is configured to:
- determine that an exception corresponding to a read or write access request for a particular set of data associated with a main memory of a host coupleable to the hybrid memory system is going to occur;
- and
- cause the particular set of data to be selectively stored in the first NVM or the second NVM of the hybrid memory system by mapping a logical block address (LBA) associated with the main memory associated with the host to the one of the first NVM or the second NVM that is configured to exhibit a lower write latency based, at least in part on a determination that executing instructions to access a portion of the main memory in which the particular set of data is maintained will cause the exception to occur.
2 more elements
An apparatus, comprising:
- a hybrid memory system comprising a first non-volatile memory (NVM) resource, a second NVM resource, and a controller,
- wherein the controller is configured to:
- cause a portion of the hybrid memory system to be allocated for use in a code paging operation;
- cause a portion of a memory associated with a host to be mapped to a logical block addressing (LBA) range;
- cause the LBA range to be mapped to the allocated portion of the hybrid memory system;
- determine that an exception corresponding to a read or write access request for a particular set of data associated with a main memory of the host coupleable to the hybrid memory system is going to occur;
- and
- cause the particular set of data to be selectively stored in the first NVM or the second NVM of the hybrid memory system by mapping a LBA associated with the main memory of the host to the one of the first NVM or the second NVM that is configured to exhibit a lower write latency based, at least in part on performance of the code paging operation and a determination that executing instructions to access a portion of the main memory in which the particular set of data is maintained will cause the exception to occur.
5 more elements
Dependencies are inferred from the claim text.