Supporting adaptive shared cache management
AssigneeIntel Corporation
InventorsCarl J. Beckmann, Robert G. Blankenship, Chyi-Chang Miao, Chitra Natarajan, Anthony-Trung D. Nguyen
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntel Corporation
InventorsCarl J. Beckmann, Robert G. Blankenship, Chyi-Chang Miao, Chitra Natarajan, Anthony-Trung D. Nguyen
Estimating the term…
Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.
A processing device comprising:
A method comprising:
A system comprising:
Dependencies are inferred from the claim text.