Scalably mechanism to implement an instruction that monitors for writes to an address

A system to process instructions comprising:

• an interconnect;
• a processor coupled with the interconnect, the processor including:
• a cache portion control unit including a first address monitor including at least some circuitry and corresponding to and coupled with a first cache portion of a distributed cache and having a total number of address monitor storage locations that is less than a total number of hardware threads of the processor, the distributed cache including a plurality of cache portions each during operation mapped to a non-overlapping range of addresses, each address monitor storage location to store an address that the cache portion control unit is to monitor writes to, and an identifier associated with a logical processor for which the writes to the address are to be monitored, wherein the address monitor storage locations are distinct from the distributed cache;
• a core interface unit including a second address monitor including at least some circuitry and corresponding to and coupled with a first core and having a same number of address monitor storage locations as a number of one or more hardware threads of the first core, each address monitor storage location of the second address monitor to store an address, which the core interface unit is to monitor writes to, and a monitor state, for a different corresponding hardware thread of the first core;
• and
• an address monitor storage overflow unit of the cache portion control unit which includes at least some circuitry and coupled with the first address monitor to detect that all address monitor storage locations of the first address monitor are used and none are available to store a first address for a first monitor request and to implement an address monitor storage overflow policy when said all of the address monitor storage locations of the first address monitor are used and none are available to store the first address for the first monitor request, wherein the address monitor storage overflow policy when implemented is to cause a plurality of logical processors to be signaled when a write to a given address being monitored is detected, but only a single logical processor is to be signaled when the write to the given address is detected when the address monitor storage overflow policy is not implemented;
• a dynamic random access memory coupled with the interconnect;
• a wireless communication device coupled with the interconnect;
• and
• an image capture device coupled with the interconnect.

A method in a processor comprising:

• receiving a first instruction indicating an address and indicating to monitor for writes to the address at a first logical processor of a first core of a multi-core processor;
• and
• in response to the first instruction:
• storing the address indicated by the first instruction in a first core-side address monitor storage location of a plurality of core-side address monitor storage locations that correspond to the first core, wherein a number of the plurality of core-side address monitor storage locations is equal to a number of logical processors of the first core;
• storing the address indicated by the first instruction in a first cache-side address monitor storage location of a plurality of cache-side address monitor storage locations that correspond to a first cache portion of a distributed cache that includes a plurality of cache portions that each are mapped to a non-overlapping range of addresses, wherein the plurality of the cache-side address monitor storage locations are not part of the distributed cache, and wherein a total number of the plurality of cache-side address monitor storage locations is less than a total number of logical processors of the multi-core processor;
• storing an identifier of the first core in the first cache-side address monitor storage location;
• activating the processor to monitor for writes to the address;
• changing a monitor state to a speculative state;
• signaling only the first core when a write to the address is detected;
• receiving a second instruction indicating a second address and indicating to monitor for writes to the second address at the first logical processor;
• determining that there are no available cache-side address monitor storage locations among the plurality of cache-side address monitor storage locations that correspond to the first cache portion;
• and
• determining to enter a cache-side address monitor storage location overflow mode;
• signaling a plurality of cores, when in the overflow mode, when a write to the second address is detected.